Method and apparatus for data scrambling

An apparatus for scrambling and descrambling data in a computer system, comprising:

• a first chip including:
• a first high speed inter chip (IP) link circuit located on a first chip;
• a first serializer/deserializer (SERDES) physical (PHY) circuit on the first chip, communicatively coupled with the first high speed link IP circuit;
• and
• a second chip including:
• a second SERDES PHY circuit,
• wherein the first high speed link IP circuit transmits data to the first SERDES PHY circuit located on the first chip, the first high speed link IP indicating whether the data is scrambled,
• on a condition that the data is non-scrambled, the first SERDES PHY scrambles the received non-scrambled data and transmits the scrambled data to the second chip,
• on a condition that the data received from the first high speed IP link circuit is scrambled, transmitting the scrambled data to the second chip,
• the second SERDES PHY circuit located on the second chip receives the scrambled data, descrambles the scrambled data, and transmits the non-scrambled data to a third circuit for further processing or transmission.