Time-to-digital conversion circuit
AssigneeSharp Kabushiki Kaisha
InventorYoshihisa Fujimoto
Life of this patent
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Abstract
A time-to-digital conversion circuit includes; an oscillator circuit that outputs a plurality of phase signals different from each other, a counter that counts a number of edges of at least one phase signal among the plurality of phase signals and outputs a count signal, a phase sampling circuit that samples the value of each of the plurality of phase signals at a stop time point and outputs a stop phase signal, a start phase signal generating circuit that outputs a start phase signal, and an output circuit that, based on the count signal, the stop phase signal, and the start phase signal, generates an output signal, the output signal being a digital signal indicating a time period from a start time point to a stop time point.
Claims3
A time-to-digital conversion circuit to which a start signal and a stop signal are input, comprising:
- an oscillator circuit that outputs a plurality of phase signals different from each other, begins oscillating in accordance with the start signal and stops oscillating in accordance with the stop signal;
- and
- a counter that counts a number of edges of at least one phase signal among the plurality of phase signals and outputs a count signal indicating the number of edges,
- wherein a phase of the oscillator circuit is specified in accordance with a value of each of the plurality of phase signals, and
- wherein the phase at a start time point at which the start signal is input and the phase at a stop time point at which the stop signal is input are referred to as a start phase and a stop phase, respectively,
- the time-to-digital conversion circuit further comprising:
- a phase sampling circuit that samples the value of each of the plurality of phase signals at the stop time point and outputs a stop phase signal indicating the stop phase;
- a start phase signal generating circuit that outputs a start phase signal for specifying the start phase;
- and
- an output circuit that, based on the count signal, the stop phase signal, and the start phase signal, generates an output signal, the output signal being a digital signal indicating a time period from the start time point to the stop time point.
Dependencies are inferred from the claim text.