System and method of monitoring a switching transistor

A method comprising:

• using a monitoring circuit disposed on a monolithic integrated circuit, monitoring an output signal of a first switching transistor for a first output edge transition at a monitoring terminal of the monolithic integrated circuit;
• using a time measuring circuit disposed on the monolithic integrated circuit, measuring a first time delay between a first input edge transition of a first drive signal and the first output edge transition, wherein the first drive signal is configured to cause a change of state of the first switching transistor;
• using an analysis circuit disposed on the monolithic integrated circuit, comparing the measured first time delay with a first predetermined threshold to form a first comparison result;
• indicating a first error condition based on the first comparison result;
• and
• performing a power-up test comprising:
• before measuring the first time delay:
• deactivating the first switching transistor via a first drive circuit disposed on the monolithic integrated circuit, and
• using a current source, applying a first current at the monitoring terminal.

An integrated circuit comprising:

• a monitoring circuit having an input coupled to a monitoring terminal configured to be coupled to an output terminal of a first switching transistor, wherein the monitoring circuit is configured to monitor an output signal at the monitoring terminal for a first output edge transition;
• a time measuring circuit coupled to the monitoring circuit, wherein the time measuring circuit is configured to measure a first time delay between a first input edge transition of a first drive signal and the first output edge transition, and wherein the first drive signal is configured to cause a change of state of the first switching transistor;
• and
• an analysis circuit coupled to the time measuring circuit and configured to compare the measured first time delay with a first predetermined threshold to form a first comparison result and to indicate a first error condition based on the first comparison result, wherein:
• the monitoring terminal is further configured to be coupled to an output terminal of a second switching transistor,
• the monitoring circuit is further configured to monitor the output signal at the monitoring terminal for a second output edge transition,
• the time measuring circuit is further configured to measure a second time delay between a second input edge transition of a second drive signal and the second input edge transition, wherein the second drive signal is configured to cause a change of state of the second switching transistor, and
• the analysis circuit is further configured to compare the measured second time delay with a second predetermined threshold to form a second comparison result and to indicate a second error condition based on the second comparison result.

An integrated circuit comprising:

• a monitoring circuit having an input coupled to a monitoring terminal configured to be coupled to an output terminal of a first switching transistor, wherein the monitoring circuit is configured to monitor an output signal at the monitoring terminal for a first output edge transition;
• a time measuring circuit coupled to the monitoring circuit, wherein the time measuring circuit is configured to measure a first time delay between a first input edge transition of a first drive signal and the first output edge transition, and wherein the first drive signal is configured to cause a change of state of the first switching transistor;
• an analysis circuit coupled to the time measuring circuit and configured to compare the measured first time delay with a first predetermined threshold to form a first comparison result and to indicate a first error condition based on the first comparison result;
• comprising a first drive circuit disposed on the integrated circuit, wherein the first drive circuit has an output coupled to a first drive terminal configured to be coupled to a control terminal of the first switching transistor, and the first drive circuit is configured to change the state of the first switching transistor based on the first drive signal;
• a test current source coupled to the monitoring terminal;
• and
• control logic coupled to the test current source, the analysis circuit and the first drive circuit, wherein the control logic is configured to operate the integrated circuit in a test mode by deactivating the first switching transistor via the first drive circuit and applying a first current to the monitoring terminal via the test current source prior to measuring the first time delay.

A motor system comprising:

• a first switching transistor;
• a second switching transistor;
• at least one motor control circuit disposed on a monolithic integrated circuit, the at least one motor control circuit comprising:
• a first drive circuit having an output coupled to a control terminal of the first switching transistor, wherein the first drive circuit is configured to receive a first drive input signal having a first input edge transition and to generate a first drive signal based on the first drive input signal, and wherein the first drive signal is configured to cause a change of state of the first switching transistor;
• a second drive circuit having an output coupled to a control terminal of the second switching transistor, wherein the second drive circuit is configured to receive a second drive input signal having a second input edge transition and to generate a second drive signal based on the second drive input signal, and wherein the second drive signal is configured to cause a change of state of the second switching transistor;
• a comparator circuit having an input coupled to an output terminal of the first switching transistor and an output terminal of the second switching transistor, wherein the comparator circuit is configured to monitor an output signal at a monitoring terminal for a first output edge transition and a second output edge transition;
• a counter circuit coupled to the first drive circuit, the second drive circuit, and the comparator circuit, wherein the counter circuit is configured to measure a first time delay between the first input edge transition and the first output edge transition and to measure a second time delay between the second input edge transition and the second output edge transition;
• and
• an analysis circuit coupled to the counter circuit and configured to:
• compare the measured first time delay with a first predetermined threshold to form a first comparison result,
• compare the measured second time delay with a second predetermined threshold to form a second comparison result,
• indicate a first error condition based on the first comparison result, and
• indicate a second error condition based on the second comparison result.