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US 10,895,599 B2Granted
Semiconductor apparatus
AssigneeSK hynix Inc.
InventorSoo Young Jang
Life of this patent
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Abstract
A semiconductor apparatus includes a test entry control block configured to generate a plurality of trigger signals and a reset signal according to a test setting command and addresses; and a test entry signal generation block configured to enable a test entry signal when the plurality of trigger signals are sequentially enabled.
Claims7
A semiconductor apparatus comprising:
- a test entry control block configured to generate a plurality of trigger signals in a test setting command and a plurality of addresses and generate a reset signal in response to a normal command, the test setting command and the plurality of addresses;
- a test entry signal generation block configured to enable or disable a test entry signal in response to the reset signal when the plurality of trigger signals are sequentially enabled,
- wherein the test entry control block sequentially enables the plurality of trigger signals when the test setting command and the addresses with pluralities of predetermined code values are inputted.
A semiconductor apparatus comprising:
- a test entry control block configured to generate a plurality of trigger signals and a reset signal according to a test setting command and addresses;
- and
- a test entry signal generation block configured to enable a test entry signal when the plurality of trigger signals are sequentially enabled,
- wherein the test entry control block selectively enables the plurality of trigger signals whenever the test setting command and the addresses with pluralities of predetermined code values are inputted.
1 more element
Dependencies are inferred from the claim text.