Modulation circuitry with N.5 division
AssigneeIntel IP Corporation
InventorsGeorgios Yorgos Palaskas, Paolo Madoglio, Dirk Friedrich
Life of this patent
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Abstract
Modulation circuitry is configured to generate a phase modulated signal having an output frequency that corresponds to a local oscillator (LO) signal divided by N.5. A phase locked loop (PLL) is configured to generate an LO signal having a frequency that is N.5 times the output frequency. Pulse circuitry configured to generate, based at least on a value of N, an edge signal including a pulse aligned with a positive edge of the LO signal and a pulse aligned with a negative edge of the LO signal. The edge signal is used to generate the phase modulated signal.
Claims25
Modulation circuitry adapted for generation of a phase modulated signal based on an N.+0.5 (N.5) division operation used in mobile communication, the modulation circuitry comprising:
- a phase locked loop (PLL) configured to generate a local oscillator (LO) signal comprising a frequency that is N.5 times an output frequency of the phase modulated signal;
- and
- pulse circuitry configured to generate, based at least on a value of N, an edge signal comprising a pulse aligned with a positive edge of the LO signal and a pulse aligned with a negative edge of the LO signal.
A method to generate a phase modulated signal comprising an output frequency that corresponds to a local oscillator (LO) signal divided by N.5, comprising:
- generating an LO signal with a frequency that is N.5 times the output frequency;
- generating a first series of pulses and a second series of pulses based on the LO signal and a value of N;
- generating an edge signal based on the first series of pulses and the second series of pulses, wherein the edge signal includes a pulse aligned with a positive edge of the LO signal and a pulse aligned with a negative edge of the LO signal;
- generating the phase modulated signal based on the edge signal;
- and
- transmitting or receiving a signal based on the phase modulated signal.
Modulation circuitry configured to generate a phase modulated signal having an output frequency that corresponds to an LO signal divided by N.5, comprising:
- pulse circuitry comprising a counter configured to generate a first series of pulses and a second series of pulses based on the LO signal;
- selector circuitry configured to receive the first series of pulses and the second series of pulses and generate an edge signal including a pulse aligned with a positive edge of the LO signal followed by a pulse aligned with a negative edge of the LO signal;
- division control circuitry, comprising:
- PLL control circuitry configured to control a phase locked loop (PLL) to generate the LO signal with a frequency that is N.5 times the output frequency;
- counter circuitry configured to control the counter based at least on a value of N.
Dependencies are inferred from the claim text.