Systems and methods of fabricating semiconductor devices

A method, comprising:

• obtaining input layout data generated based on inspecting an integrated circuit;
• extracting and superimposing first patterns corresponding to design patterns having a common shape from the input layout data;
• generating distribution data of the first patterns based on the superimposed first patterns;
• determining an evaluation contour of the design patterns based on an evaluation condition and the distribution data;
• generating output layout data based on replacing the first patterns with second patterns each having the evaluation contour;
• determining whether the inspected integrated circuit includes at least a threshold quantity and/or threshold concentration of weak points based on measuring at least one of the second patterns from the output layout data;
• and
• selectively incorporating the inspected integrated circuit into a semiconductor device based on a determination that the inspected integrated circuit includes less than the threshold quantity and/or the threshold concentration of weak points.

A method, comprising:

• obtaining input layout data generated based on inspecting an integrated circuit;
• extracting and superimposing first patterns corresponding to design patterns having a common shape from the input layout data;
• determining an evaluation contour of the design patterns based on an evaluation condition and the superimposed first patterns;
• determining whether the inspected integrated circuit includes at least a threshold quantity and/or threshold concentration of weak points based on replacing the first patterns with second patterns each having the evaluation contour and measuring at least one of the second patterns;
• and
• selectively incorporating the inspected integrated circuit into a semiconductor device based on a determination that the inspected integrated circuit includes less than the threshold quantity and/or the threshold concentration of weak points.