Fin-based fill cell optimization

A system comprising:

• a memory having computer readable instructions;
• and
• one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
• receiving a semiconductor layout comprising at least a first logic cell, a second logic cell, and a fill cell, wherein a left boundary of the fill cell is adjacent to the first logic cell and a right boundary of the fill cell is adjacent to the second logic cell;
• determining a number of active left fins, a number of active right fins, and a number of active fill cell fins, wherein the number of active left fins represents a number of active fins associated with a fin field-effect transistors (FinFET) structure of the first logic cell, the number of active right fins represents a number of active fins associated with a FinFET structure of the second logic cell, and the number of active fill cell fins represents a number of active fins associated with a FinFET structure of the fill cell, and the fill cell is a non-functional cell comprising one or more transistors corresponding to the number of active fill cell fins;
• comparing the number of active left fins, the number of active right fins, and the number of active fill cell fins to a set of fin rules;
• and
• responsive to determining that the semiconductor layout violates the set of fin rules based on the comparison, modifying the semiconductor layout to change the number of active fill cell fins to satisfy the set of fin rules.

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer processor to cause the computer processor to perform a method comprising:

• receiving a semiconductor layout comprising at least a first logic cell, a second logic cell, and a fill cell, wherein a left boundary of the fill cell is adjacent to the first logic cell and a right boundary of the fill cell is adjacent to the second logic cell;
• determining a number of active left fins, a number of active right fins, and a number of active fill cell fins, wherein the number of active left fins represents a number of active fins associated with a fin field-effect transistors (FinFET) structure of the first logic cell, the number of active right fins represents a number of active fins associated with a FinFET structure of the second logic cell, and the number of active fill cell fins represents a number of active fins associated with a FinFET structure of the fill cell, and the fill cell is a non-functional cell comprising one or more transistors corresponding to the number of active fill cell fins;
• comparing the number of active left fins, the number of active right fins, and the number of active fill cell fins to a set of fin rules;
• and
• responsive to determining that the semiconductor layout violates the set of fin rules based on the comparison, modifying the semiconductor layout to change the number of active fill cell fins to satisfy the set of fin rules.