Random forest model for prediction of chip layout attributes

A method comprising:

• receiving an input at a machine learning model, wherein the input describes a pattern within a particular chip layout, the machine learning model comprises a random forest model trained using training data based on a plurality of sets of silicon data, each of the sets of silicon data describe processing attributes observed in association with previous performance of a particular one of a set of fabrication steps in a chip fabrication process involving other chip layouts, and the training data further describes geometric features of the corresponding to other chip layouts, wherein the random forest model comprises a plurality of decision tree models and a voting block to implement a particular voting algorithm, and the other chip layouts are different from the particular chip layout;
• generating results at each of the plurality of decision tree models, wherein the results identify predicted processing attributes of performance of the particular fabrication step based on the pattern;
• and
• performing a vote using the voting block to determine, from the results, an output of the machine learning model, wherein the output identifies a predicted attribute of performance of the particular fabrication step based on the pattern of the particular chip layout.

A system comprising:

• at least one data processor;
• a memory;
• and
• a machine learning engine, executable by the data processor to:
• access a particular machine learning model, wherein the particular machine learning model comprises a random forest model trained based on a plurality of sets of silicon data generated from tests of previously fabricated chips, the particular machine model corresponds to a particular fabrication step in a chip fabrication process, and the plurality of sets of silicon data describe geometric features of chip layouts used in the previously fabricated chips;
• provide an input to the random forest model, wherein the input comprises a feature set of a pattern within a particular chip layout, and the feature set identifies geometric attributes of polygonal elements within the pattern;
• and
• generate a result at the random forest model based on the input, wherein the result identifies a predicted attribute of performance of the particular fabrication step based on the pattern based on the plurality of sets of silicon data, and the result is generated based at least in part on determining, within the random forest model, that geometric attributes of the pattern were included in the previously fabricated chips, wherein the previously fabricated chips have chip layouts different from the particular chip layout.