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US 10,885,258 B1Granted
Fixing ESD path resistance errors in circuit design layout
AssigneeSynopsys, Inc.
InventorDe-Shiuan Chiou
Life of this patent
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AssigneeSynopsys, Inc.
InventorDe-Shiuan Chiou
Estimating the term…
A physical verification tool for debugging ESD ground path resistance violations in ESD protection circuits. The ESD ground path is modeled and partitioned into component path structures (polygons) that are disposed in associated design layers. A total ESD ground path resistance is then calculated and compared with a maximum allowable resistance value defined by an ESD protection rule. When the ESD ground path is non-compliant, a resistance contribution ratio is determined for each polygon and/or for each layer, for example, by applying nodal analysis to the ESD ground path model. Resistance contribution ratios are then calculated for each polygon and/or for each layer, and most-problematic polygons and/or layers are identified by way of having the highest resistance contribution ratio values. A report (e.g., a table or graphical visualization) is then generated that prioritizes or emphasizes (e.g., by way of a bolder contrast or brighter color) the most-problematic layer and/or polygon.
A method for analyzing an electrostatic discharge-to-ground (ESD ground) path of a target circuit design during a physical verification process implemented in a computing system, said ESD ground path including a plurality of component path structures disposed in a plurality of layers, each said component path structure being disposed in an associated said layer, said method comprising:
A method for analyzing an electrostatic discharge-to-ground (ESD ground) path of a target circuit design during a physical verification process implemented in a computing system, said method comprising:
A computing system comprising a non-transitory computer-readable medium storing instructions that, when implemented by a processor of the computing system, cause the processor to perform a physical verification process configured to verify a layout description of a target circuit design, said physical verification process including operations for analyzing an electrostatic discharge-to-ground (ESD ground) path of said target circuit design, said ESD ground path including a plurality of component path structures disposed in a plurality of layers, each said component path structure being disposed in an associated said layer, said operations comprising:
Dependencies are inferred from the claim text.