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US 10,885,253 B2Granted
System and method for determining dimensional range of repairable defects by deposition and etching in a virtual fabrication environment
AssigneeCoventor, Inc.
InventorsDaniel Sobieski, Rich Wise, Yang Pan, David M. Fried, Jiangjiang Gu
Life of this patent
Estimating the term…
Abstract
A virtual fabrication environment for semiconductor device fabrication that determines a lowest lithography exposure dose range in which one or more defects are still reparable by deposition and etch operations is discussed. Further techniques for repairing line edge roughness caused by lithography are described.
Claims21
A non-transitory computer-readable medium holding computer-executable instructions for performing defect mitigation caused by lithography exposure in a virtual semiconductor fabrication environment, the instructions when executed causing the computing device to:
- receive or create a physical design pattern in a virtual fabrication environment to model defects from lithography exposure during fabrication of a semiconductor device structure;
- receive in a virtual fabrication environment material selectivity and resist profile information for use in virtual fabrication of a 3D model of the semiconductor device structure;
- perform in the virtual fabrication environment a virtual experiment performing a plurality of virtual fabrication runs using the physical design pattern and material selectivity and resist profile information, the virtual experiment creating a plurality of 3D models of the semiconductor device structure and performing a plurality of deposition and etching operations on one or more defects in the plurality of 3D models using one or more experimentally-controlled parameters;
- determine a remaining defect quantity for each of the plurality of 3D models created by the virtual experiment following the performing of the plurality of deposition and etching operations;
- and
- identify, based on the remaining defect quantity for each of the plurality of 3D models created by the virtual experiment, a lowest lithography exposure dose or dose range at which the one or more defects are repairable by the plurality of deposition and etching operations.
3 more elements
A computing device-implemented method for performing defect mitigation caused by lithography exposure in a virtual semiconductor fabrication environment, the computing device including one or more processors, the method comprising:
- receiving or creating a physical design pattern in a virtual fabrication environment to model defects from lithography exposure during fabrication of a semiconductor device structure;
- receiving in a virtual fabrication environment material selectivity and resist profile information for use in virtual fabrication of a 3D model of the semiconductor device structure;
- performing in the virtual fabrication environment a virtual experiment performing a plurality of virtual fabrication runs using the physical design pattern and material selectivity and resist profile information, the virtual experiment creating a plurality of 3D models of the semiconductor device structure and performing a plurality of deposition and etching operations on one or more defects in the plurality of 3D models using one or more experimentally-controlled parameters;
- determining a remaining defect quantity for each of the plurality of 3D models created by the virtual experiment following the performing of the plurality of deposition and etching operations;
- and
- identifying, based on the remaining defect quantity for each of the plurality of 3D models created by the virtual experiment, a lowest lithography exposure dose or dose range at which the one or more defects are repairable by the plurality of deposition and etching operations.
3 more elements
A virtual fabrication system, comprising:
- at least one computing device equipped with one or more processors and configured to generate a virtual fabrication environment that includes a defect mitigation module, the defect mitigation module when executing:
- receives or creates a physical design pattern in a virtual fabrication environment to model defects from lithography exposure during fabrication of a semiconductor device structure;
- receives in a virtual fabrication environment material selectivity and resist profile information for use in virtual fabrication of a 3D model of the semiconductor device structure;
- performs in the virtual fabrication environment a virtual experiment performing a plurality of virtual fabrication runs using the physical design pattern and material selectivity and resist profile information, the virtual experiment creating a plurality of 3D models of the semiconductor device structure and performing a plurality of deposition and etching operations on one or more defects in the plurality of 3D models using one or more experimentally-controlled parameters;
- determines a remaining defect quantity for each of the plurality of 3D models created by the virtual experiment following the performing of the plurality of deposition and etching operations;
- and
- identifies, based on the remaining defect quantity for each of the plurality of 3D models created by the virtual experiment, a lowest lithography exposure dose or dose range at which the one or more defects are repairable by the plurality of deposition and etching operations,
- and
- a display surface in communication with the at least one computing device, the display surface configured to display the 3D model in a 3D view.
6 more elements
Dependencies are inferred from the claim text.