Clock gate placement with data path awareness
AssigneeCadence Design Systems, Inc.
InventorsDavid White, Andrew Mark Chapman, Thomas Andrew Newton, Zhuo Li
Life of this patent
Estimating the term…
Abstract
Electronic design automation systems, methods, and media are presented for clock gate placement with data path awareness. One embodiment involves accessing a circuit design with a clock tree, clock gates, and an initial movement area. A set of positions for a set of data path connection points associated with the data routing lines are identified, along with an expansion direction from the initial placement position toward the set of positions for the set of data path connection points, and the initial movement is expanded to consider additional placement options for the clock gate based on the data path connection points.
Claims20
A computer-implemented method comprising:
- accessing, by one or more hardware processors, a circuit design stored in memory, the circuit design comprising a clock path for a clock tree, a data path, at least a first clock gate coupled to the clock path and the data path, and an initial placement position for the first clock gate;
- identifying, using the one or more hardware processors, an initial movement area for analyzing an impact of adjusting the initial placement position for the first clock gate to an updated placement position within the initial movement area on a total wirelength for clock routing lines from the first clock gate to the clock path and data routing lines from the first clock gate to the data path;
- identifying, using the one or more hardware processors, a set of positions for a set of data path connection points associated with the data routing lines;
- identifying, using the one or more hardware processors, an expansion direction from the initial placement position toward the set of positions for the set of data path connection points;
- expanding the initial movement area toward the expansion direction, using the one or more hardware processors, to generate an extended movement area;
- analyzing, using the one or more hardware processors, one or more placement positions in the extended movement area;
- and
- selecting, using the one or more hardware processors, a first placement position for the first clock gate based on the analyzing the one or more placement positions.
A device comprising:
- a memory configured to store a circuit design, the circuit design comprising a clock path for a clock tree, a data path, at least a first clock gate coupled to the clock path and the data path, and an initial placement position for the first clock gate;
- one or more processors coupled to the memory and configured to perform operations comprising:
- identifying an initial movement area for analyzing an impact of adjusting the initial placement position for the first clock gate to an updated placement position within the initial movement area on a total wirelength for clock routing lines from the first clock gate to the clock path and data routing lines from the first clock gate to the data path;
- identifying a set of positions for a set of data path connection points associated with the data routing lines;
- identifying an expansion direction from the initial placement position toward the set of positions for the set of data path connection points;
- analyzing a set of placement positions comprising at least a first placement position outside the initial movement area, wherein a location of the first placement position is based on the expansion direction;
- and
- selecting the first placement position for the first clock gate based on the analyzing the set of placement positions.
A non-transitory computer-readable medium comprising instructions that, when executed by one or more processors of an electronic design automation (EDA) computing device, cause the device to perform operations comprising:
- accessing a circuit design stored in memory, the circuit design comprising a clock path for a clock tree, a data path, at least a first clock gate coupled to the clock path and the data path, and an initial placement position for the first clock gate;
- identifying an initial movement area for analyzing an impact of adjusting the initial placement position for the first clock gate to an updated placement position within the initial movement area on a total wirelength for clock routing lines from the first clock gate to the clock path and data routing lines from the first clock gate to the data path;
- identifying a set of positions for a set of data path connection points associated with the data routing lines;
- identifying an expansion direction from the initial placement position toward the set of positions for the set of data path connection points;
- expanding the initial movement area toward the expansion direction to generate an extended movement area;
- analyzing one or more placement positions in the extended movement area;
- and
- selecting a first placement position for the first clock gate based on the analyzing the one or more placement positions.
Dependencies are inferred from the claim text.