Multi-level hierarchical large block synthesis (hLBS) latch optimization

A system to develop an integrated circuit, the system comprising:

• a child placement module configured to place in a parent macro at least one child macro that contains therein at least one child logic circuit component, the parent macro having a first hierarchical level assigned thereto and the child macro having a second hierarchical level assigned thereto that is lower than the first hierarchical level assigned to the parent macro,
• a timing analysis module configured to detect a timing fault in response to performing a first parent-level optimization process on the parent macro;
• and
• a component targeting module configured to extract from the child macro a targeted logic circuit component from among the at least one child logic circuit component, and to place the targeted logic circuit component in the parent macro,
• wherein the timing analysis module performs a second parent-level optimization process on the parent macro that resolves the timing fault based on the placement of the targeted logic circuit component in the parent macro.

A computer program product for developing an integrated circuit development, the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to perform a method comprising:

• placing in a parent macro, via a computer processor, at least one child macro that contains therein at least one child logic circuit component, the parent macro having a first hierarchical level assigned thereto and the child macro having a second hierarchical level assigned thereto that is lower than the first hierarchical level assigned to the parent macro;
• detecting, via the computer processor, a timing fault in response to performing a first parent-level optimization process on the parent macro;
• extracting from the child macro, via the computer processor, a targeted logic circuit component from among the at least one child logic circuit component, and placing the targeted logic circuit component in the parent macro;
• and
• performing a second parent-level optimization process on the parent macro that resolves the timing fault based on the placement of the targeted logic circuit component in the parent macro.