Method for modeling glitches during circuit simulation

A computer-implemented method comprising:

• simulating a circuit design including a cell having an input node and an output node respectively operably coupled to corresponding first and second sections of a signal path, said cell including a logic function configured to generate output signal pulses in response to corresponding input signal pulses transmitted on the first signal path section to said input node;
• modifying the circuit design to include a glitch scaling module connected in parallel with said logic function between said input node and said output node of said cell;
• performing a simulated operation of said circuit design such that a plurality of input signal pulses are transmitted on said first signal path section to the input node of the cell, and such that said glitch scaling module performs a glitch scaling process including:
• determining an input duration of said each input signal pulse transmitted on a first section of said signal path to said input node of said cell;
• utilizing said determined input duration to identify when said each input signal pulse is a glitch;
• assigning a cell-type-specific scaling factor value to said each input signal pulse that is identified as a scalable glitch;
• and
• controlling said cell such that an output duration of an output pulse signal generated in response to said identified scalable glitch and passed from said output node on the second section of said signal path is determined by said input duration and said assigned cell-type-specific scaling factor value.

A non-transitory, computer-readable medium comprising stored instructions configured such that, when the stored instructions are executed by a processor, cause the processor to execute operations including:

• simulating a circuit design including a cell having an input node and an output node respectively operably coupled to corresponding first and second sections of a signal path, said cell including a logic function configured to generate output signal pulses in response to corresponding input signal pulses transmitted on the first signal path section to said input node;
• modifying the circuit design to include a glitch scaling module connected in parallel with said logic function between said input node and said output node of said cell;
• performing a simulated operation of said circuit design such that a plurality of input signal pulses are transmitted on said first signal path section to the input node of the cell, and such that said glitch scaling module performs a glitch scaling process including:
• determining an input duration of said each input signal pulse transmitted on a first section of said signal path to said input node of said cell;
• utilizing said determined input duration to identify when said each input signal pulse is a glitch;
• assigning a cell-type-specific scaling factor value to said each input signal pulse that is identified as a scalable glitch;
• and
• controlling said cell such that an output duration of an output pulse signal generated in response to said identified scalable glitch and passed from said output node on the second section of said signal path is determined by said input duration and said assigned cell-type-specific scaling factor value, and
• generating toggle count including a total number of output signal pulses generated by said cell on said second signal line path.