Test pattern, test method for semiconductor device, and computer-implemented method for designing integrated circuit layout

A test method for a semiconductor device, the test method comprising:

• preparing a substrate including a device region and a test region;
• forming a plurality of first metal interconnects with a first width in a first interconnect layer of the test region, the plurality of first metal interconnects extending in a first direction and having discontinuous regions spaced apart by a first space;
• forming a metal connection line in a second interconnect layer of the test region, the metal connection line extending in the first direction;
• forming a plurality of second metal interconnects with a second width in the second interconnect layer of the test region, the plurality of second metal interconnects extending in a second direction perpendicular to the first direction and branching from the metal connection line;
• forming a plurality of via structures with a third width in a first via layer of the test region around an intersection region having the first width of the first metal interconnect and the second width of the second metal interconnect, the plurality of via structures extending in a third direction perpendicular to the first direction and the second direction;
• forming first pads electrically connected with the plurality of first metal interconnects and a second pad electrically connected with the metal connection line;
• providing an electric signal to the second pad and one of the first pads;
• and
• examining failures of the plurality of first metal interconnects, the plurality of second metal interconnects, and the plurality of via structures using the electric signal.