Logic partition reporting for integrated circuit design

A system comprising:

• a memory having computer readable instructions;
• and
• one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
• generating a physical domain representation of an integrated circuit (IC) design based on a logic domain representation of the IC design, wherein the logic domain representation comprises a plurality of logic partitions, and wherein the physical domain representation comprises a plurality of logic clusters, each of the plurality of logic clusters corresponding to a respective logic partition of the plurality of logic partitions, wherein each of the plurality of logic clusters comprises a respective plurality of IC elements corresponding to the respective logic partition;
• assigning a logic partition identifier to each IC element of the plurality of IC elements in the physical domain representation, wherein the logic partition identifier of an IC element corresponds to a logic partition of the plurality of logic partitions, and wherein each IC element comprises a plurality of pins;
• assigning a pin name to each of the plurality of pins corresponding to the plurality of IC elements, wherein a pin name of a pin of the plurality of pins is derived based on the logic partition identifier of the IC element associated with the pin;
• and
• generating a timing report for a logic cluster of the IC design based on the logic partition identifiers and the pin names of the IC elements in the logic cluster, wherein the timing report comprises slack information, slew information, pin names, gate delay information, net delay information, and a physical location of a gate.

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising:

• generating a physical domain representation of an integrated circuit (IC) design based on a logic domain representation of the IC design, wherein the logic domain representation comprises a plurality of logic partitions, and wherein the physical domain representation comprises a plurality of logic clusters, each of the plurality of logic clusters corresponding to a respective logic partition of the plurality of logic partitions, wherein each of the plurality of logic clusters comprises a respective plurality of IC elements corresponding to the respective logic partition;
• assigning a logic partition identifier to each IC element of the plurality of IC elements in the physical domain representation, wherein the logic partition identifier of an IC element corresponds to a logic partition of the plurality of logic partitions, and wherein each IC element comprises a plurality of pins;
• assigning a pin name to each of the plurality of pins corresponding to the plurality of IC elements, wherein a pin name of a pin of the plurality of pins is derived based on the logic partition identifier of the IC element associated with the pin;
• and
• generating a timing report for a logic cluster of the IC design based on the logic partition identifiers and the pin names of the IC elements in the logic cluster, wherein the timing report comprises slack information, slew information, pin names, gate delay information, net delay information, and a physical location of a gate.