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US 10,885,004 B2Granted
Method and apparatus to manage flush of an atomic group of writes to persistent memory in response to an unexpected power loss
AssigneeIntel Corporation
InventorsKarthik Kumar, Francesc Guim Bernat, Thomas Willhalm, Mark A. Schmisseur, Benjamin Graniello
Life of this patent
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Abstract
A group of cache lines in cache may be identified as cache lines not to be flushed to persistent memory until all cache line writes for the group of cache lines have been completed.
Claims18
A processor comprising:
- a cache comprising at least one cache line;
- and
- a core coupled to the cache, the core comprising:
- an execution unit, the execution unit to set a lock in response to executing a first instruction, the lock to mark a group of cache lines in the cache not to be flushed to a persistent memory until all cache line writes for the group of cache lines have been completed, the persistent memory coupled to the processor, the execution unit to store data to be written to the persistent memory to a cache line in the group of cache lines and to set a bit in the cache line to prevent a flush of the cache line to the persistent memory in an event of a power failure while the lock is set.
1 more element
A system comprising:
- a persistent memory;
- and
- a processor coupled to the persistent memory, the processor comprising:
- a cache comprising at least one cache line;
- and
- a core coupled to the cache, the core comprising:
- an execution unit, the execution unit to set a lock in response to executing a first instruction, the lock to mark a group of cache lines in the cache not to be flushed to the persistent memory until all cache line writes for the group of cache lines have been completed, the execution unit to store data to be written to the persistent memory to a cache line in the group of cache lines and to set a bit in the cache line to prevent a flush of the cache line to the persistent memory in an event of a power failure while the lock is set.
4 more elements
A method comprising:
- storing data to be written to a persistent memory in a cache line in a cache in a processor;
- executing a first instruction, by an execution unit in a core in the processor, to set a lock to mark a group of cache lines in the cache not to be flushed to the persistent memory until all cache line writes for the group of cache lines have been completed;
- and
- storing data to be written to the persistent memory to a cache line in the group of cache lines and setting a bit in the cache line to prevent a flush of the cache line to the persistent memory in an event of a power failure while the lock is set.
1 more element
Dependencies are inferred from the claim text.