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US 10,884,970 B2Granted
Techniques for coalescing doorbells in a request message
AssigneeIntel Corporation
InventorsTomasz Kantecki, Ben-Zion Friedman, Niall D. McDonnell, Bruce Richardson
Life of this patent
Estimating the term…
Abstract
Examples include techniques for coalescing doorbells in a request message. Example techniques include gathering doorbells to access a device. The gathered are combined in a cache line structure and the cache line structure is written to a cache or buffer for a central processing unit in a single write operation.
Claims22
An apparatus comprising:
- circuitry for a computing platform, the circuitry to include a central processing unit (CPU) cache;
- doorbell logic for execution by the circuitry to generate a plurality of doorbells targeted to a respective plurality of memory rings or queues for a device on the computing platform communicatively coupled with the circuitry via a link arranged to operate according to a peripheral component interconnect express (PCIe) specification;
- combine logic for execution by the circuitry to combine the plurality of doorbells in a cache line structure that includes separate information for each doorbell, the cache line structure to have a size of 64 bytes;
- and
- write logic for execution by the circuitry to write the cache line structure to the CPU cache in a single write operation to cause the plurality of doorbells to be posted to the respective plurality of memory rings or queues.
2 more elements
A method comprising:
- generating a plurality of doorbells targeted to a respective plurality of memory rings or queues for a device on a computing platform operating according to a peripheral component interconnect express (PCIe) specification;
- combining the plurality of doorbells in a cache line structure that includes separate information for each doorbell, the cache line structure having a size of 64 bytes;
- and
- writing the cache line structure to a cache or buffer for a central processing unit (CPU) of the computing platform in a single write operation to cause the plurality of doorbells to be posted to the respective plurality of memory rings or queues.
1 more element
At least one machine readable medium comprising a plurality of instructions that in response to being executed by a system at a computing platform cause the system to:
- generate a plurality of doorbells targeted to a respective plurality of memory rings or queues for a device on the computing platform, the device to operate according to a peripheral component interconnect express (PCIe) specification;
- combine the plurality of doorbells in a cache line structure that includes separate information for each doorbell, the cache line structure to have a size of 64 bytes;
- and
- write the cache line structure to a cache or buffer for a central processing unit (CPU) of the computing platform in a single write operation to cause the plurality of doorbells to be posted to the respective plurality of memory rings or queues.
1 more element
Dependencies are inferred from the claim text.