US 10,884,960 B2Granted

Offloading data movement for packet processing in a network interface controller

AssigneeCisco Technology, Inc.

InventorsTanjore K. Suresh, David S. Walker, Ravi Shankar Palagummi, RaviKiran Kaidala Lakshman, Kar Wai Kam

Life of this patent

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Abstract

In one embodiment, a direct memory access (DMA) controller within a host device obtains a packet to be processed by the host device, where the host device comprises a host processor, a network interface controller (NIC), and a co-processor of the NIC, and where the co-processor is configured to perform one or more specific packet processing operations. The DMA controller may then detect a DMA descriptor of the packet, and can determine, according to the DMA descriptor, how the packet is to be moved for processing within the host device. As such, the DMA controller may then move the packet, based on the determining, to one of either a host main memory, a NIC memory, or a co-processor memory of the host device.

Claims20

Dependent claims

A method, comprising:

obtaining, at a direct memory access (DMA) controller within a host device comprising a host main memory, a packet to be processed by the host device, wherein the host device comprises:
a) a host processor, b) a network interface controller (NIC) comprising a NIC memory, and c) a co-processor of the NIC that comprises a co-processor memory that is separate from the NIC memory and configured to store data for processing by the co-processor, the co-processor memory including a base address register (BAR) space and a controller memory buffer, and wherein the co-processor is configured to perform one or more specific packet processing operations using the co-processor memory;
detecting, by the DMA controller, a DMA descriptor of the packet;
determining, by the DMA controller according to the DMA descriptor, how the packet is to be moved for processing within the host device;
and
moving the packet, by the DMA controller based on the determining, to one of the host main memory, the NIC memory, or the co-processor memory of the host device.

3 more elements

An apparatus, comprising:

a host processor configured to execute one or more processes;
a host main memory configured to store data for processing by the host processor;
a network interface controller (NIC) coupled to the host processor and configured to communicate with a network, the NIC comprising:
a) a NIC processor configured to execute one or more processes,
b) a NIC memory configured to store data for processing by the NIC processor, and
c) a co-processor configured to perform one or more specific packet processing operations using a co-processor memory, the co-processor comprising the co-processor memory that is separate from the NIC memory and configured to store data for processing by the co-processor, the co-processor memory including a base address register (BAR) space and a controller memory buffer;
and
a direct memory access (DMA) controller configured to:
obtain a packet to be processed by the apparatus;
detect a DMA descriptor of the packet;
determine, according to the DMA descriptor, how the packet is to be moved for processing within the apparatus;
and
move the packet, based on the determining, to one of the host main memory, the NIC memory, or the co-processor memory.

10 more elements

A tangible, non-transitory, computer-readable medium storing program instructions that cause a computer to execute a direct memory access (DMA) controller process, comprising:

obtaining a packet to be processed by a host device comprising a host main memory, wherein the host device comprises:
a) a host processor, b) a network interface controller (NIC) comprising a NIC memory, and c) a co-processor of the NIC that comprises a co-processor memory that is separate from the NIC memory and configured to store data for processing by the co-processor, the co-processor memory including a base address register (BAR) space and a controller memory buffer, and wherein the co-processor is configured to perform one or more specific packet processing operations using the co-processor memory;
detecting a DMA descriptor of the packet;
determining, according to the DMA descriptor, how the packet is to be moved for processing within the host device;
and
moving the packet, based on the determining, to one of either the host main memory, the NIC memory, or the co-processor memory of the host device.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/389,040Filed 19 Apr 2019
Published: US 2020/0334184 A122 Oct 2020
Granted: 5 Jan 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 13/28
For access to input/output bus: using burst mode transfer, e.g. direct memory access DMA, cycle steal
G06F 13/128
Where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine: for dedicated transfers to a network
G06F 13/4282
Bus transfer protocol, e.g. handshake; Synchronisation: on a serial bus, e.g. I2C bus, SPI bus
G06F 2213/0026
Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central…:…