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US 10,884,958 B2Granted
DIMM for a high bandwidth memory channel
AssigneeIntel Corporation
InventorsRajat Agarwal, Bill Nale, Chong J. Zhao, James A. McCall, George Vergis
Life of this patent
Estimating the term…
Abstract
A DIMM is described. The DIMM includes circuitry to multiplex write data to different groups of memory chips on the DIMM during a same burst write sequence.
Claims18
An apparatus, comprising:
- a memory controller comprising a memory channel interface to couple to a memory channel, the memory channel interface comprising a first group of data inputs/outputs (I/Os) and second group of data I/Os, the first group of data I/Os to couple to a first dual in-line memory module (DIMM) in only a point-to-point link fashion, the second group of data I/Os to couple to a second DIMM in only a point-to-point link fashion, the memory controller comprising logic circuitry to send first multiplexed write data to the first DIMM that targets different groups of memory chips on the first DIMM during a same first burst write sequence, the memory controller to also concurrently send second multiplexed write data to the second DIMM that targets different groups of memory chips on the second DIMM during a same second burst write sequence and that exists on the memory channel during a same time period that the first burst write sequence exists on the memory channel, wherein, the memory channel interface conforms to an industry standard specification, wherein, the memory channel as described by the industry standard specification comprises a first data bus that is to couple to multiple DIMMs and describes a second data bus that is to couple to the multiple DIMMs, wherein, the first group of I/Os correspond to the first data bus and the second group of I/Os correspond to the second data bus.
An apparatus, comprising:
- a dual in-line memory module (DIMM) comprising circuitry to multiplex write data to different groups of memory chips on the DIMM during a same burst write sequence of a memory channel, wherein, the DIMM is to receive some of the write data for a first of the different groups of memory chips in a portion of a single data transfer cycle of the memory channel and receive some of the write data for a second of the different groups of memory chips in another portion of the single data transfer cycle of the memory channel, wherein, the DIMM is to couple to a data bus that is to couple only to a single DIMM, wherein, the memory channel conforms to an industry standard specification that describes a respective data bus that is permitted to be a multi-drop data bus.
An apparatus, comprising:
- a memory controller comprising multiplexer circuitry to multiplex data and addresses of different ranks of memory chips on a same dual in-line memory module (DIMM) over a same read or write burst time window on a memory channel, wherein, the memory controller is to correspondingly receive or send less than a full rank width of data for a first of the ranks in a portion of a single data transfer cycle of the memory channel and correspondingly receive or send less than a full rank width of data for a second of the ranks of memory chips in another portion of the single data transfer cycle of the memory channel, wherein, transmission of the less than full rank width for the first rank and transmission of the less than full rank width for the second rank alternate on the memory channel.
Dependencies are inferred from the claim text.