Pipeline circuit architecture to provide in-memory computation functionality

A processor for performing an in-memory computation, the processor comprising:

• a processor core comprising a controller circuit;
• a pipeline circuit coupled the controller circuit, the pipeline circuit comprising:
• a first stage of multiple stages of the pipeline circuit, the multiple stages arranged in an in-series configuration, the first stage comprising:
• a first memory array to store first data provided by the controller circuit;
• and
• first circuitry coupled to perform a first in-memory computation based on a read of the first data from the first memory array, wherein the first computation comprises a first operation on first operands which are each read from a respective addressable location of the first memory array, wherein the first circuitry is further to store a first result of the first in-memory computation to the first memory array;
• an interconnect coupled to receive from the first stage second data which is based on the first result, wherein any communication between the interconnect and the controller circuit is to be via one or more of the multiple stages;
• a second stage of the multiple stages, the second stage comprising:
• a second memory array to receive and store the second data;
• and
• second circuitry coupled to access the second memory array, and to perform a second in-memory computation based on a read of the second data from the second memory array, wherein the second circuitry is to store a second result of the second in-memory computation to the second memory array, wherein the second computation comprises a second operation on second operands which are each read from a respective addressable location of the second memory array.

A method at a pipeline circuit for performing in-memory computations, the method comprising:

• receiving first data from a controller circuit coupled to the pipeline circuit, wherein the pipeline circuit comprises multiple stages arranged in an in-series configuration, the multiple stages comprising a first stage and a second stage;
• storing the first data at a first memory array of the first stage;
• performing at the first stage a first computation based on a read of the first data from the first memory array, wherein the first computation comprises a first operation on first operands which are each read from a respective addressable location of the first memory array;
• storing a first result of the first computation at the first memory array;
• communicating second data from the first stage to the second stage via a first interconnect of the pipeline circuit, wherein the second data is based on the first result, wherein any signal communication between the first interconnect and the controller circuit is to be via one or more stages of the multiple stages;
• storing the second data at a second memory array of the second stage;
• performing at the second stage a second computation based on a read of the second data from the second memory array, wherein the second computation comprises a second operation on second operands which are each read from a respective addressable location of the second memory array;
• and
• storing a second result of second computation at the second memory array.

A system comprising

• a pipeline circuit for performing an in-memory computation, the pipeline circuit comprising:
• a first stage of multiple stages of the pipeline circuit, the multiple stages arranged in an in-series configuration, the first stage comprising:
• a first interface to receive first data from a controller circuit coupled to the pipeline circuit;
• a first memory array to store the first data;
• and
• first circuitry coupled to the first memory array, the first circuitry to perform a first read of the first data from the first memory array, to perform a first computation based on the first read of the first data, and to store a first result of the first computation at the first memory array, wherein the first computation comprises a first operation on first operands which are each read from a respective addressable location of the first memory array;
• an interconnect coupled to receive from the first stage second data which is based on the first result, wherein any communication between the interconnect and the controller circuit is to be via one or more of the multiple stages;
• a second stage of the multiple stages, the second stage comprising:
• a second interface to receive the second data from the interconnect;
• a second memory array to store the second data;
• and
• second circuitry to perform a second read of the second data from the second memory array, to perform a second computation based on the second read of the second data, and to store a second result of the second computation at the second memory array, wherein the second computation comprises a second operation on second operands which are each read from a respective addressable location of the second memory array;
• and
• a display device coupled to the pipeline circuit, the display device to display an image based on a signal communicated with the pipeline circuit, the signal based on the second computation.