US 10,884,956 B2 · I/O bus shared memory system

Abstract

A memory system has a plurality of memory devices coupled with a hub in discrete and shared port arrangements. A plurality of bus lines connect the plurality of memory devices to the hub, including a first subset of bus lines connected in a point-to-point configuration between the hub and a particular memory device, and a second subset of bus lines connected to all the memory devices in the plurality of memory devices including the particular memory device. Bus operation logic is configured to use the first subset of bus lines in a first operation accessing the particular memory device while simultaneously using the second subset of bus lines in a second operation accessing a different selected memory device of the plurality of memory devices.

Claims19

Dependent claims

A hub comprising:

a set of ports including a plurality of ports;
and
bus operation logic configured to use a first subset of ports, including one or more ports of the set of ports, configured for point-to-point connections to a particular memory device in a first operation accessing the particular memory device while using a second subset of ports, including one or more ports of the set of ports, configured for shared connections to a plurality of memory devices in a second operation accessing a different selected memory device of the plurality of memory devices, where the first operation overlaps in time with the second operation, at least one port in the second subset of ports and at least one port in the first subset of ports being different ports.

A memory system comprising:

a plurality of memory devices;
a hub;
a plurality of bus lines connecting the plurality of memory devices to the hub, including a first subset of bus lines, including one or more bus lines in the plurality of bus lines, configured for point-to-point connections to a particular memory device in the plurality of memory devices, and a second subset of bus lines, including one or more bus lines in the plurality of bus lines, configured for shared connections to all the memory devices in the plurality of memory devices including the particular memory device;
and
the hub including bus operation logic configured to use the first subset of bus lines in a first operation accessing the particular memory device while using the second subset of bus lines in a second operation accessing a different selected memory device of the plurality of memory devices, where the first operation overlaps in time with the second operation, at least one bus line in the second subset of bus lines and at least one bus line in the first subset of bus lines being different bus lines.

2 more elements

Dependencies are inferred from the claim text.

I/O bus shared memory system

Life of this patent

I/O bus shared memory system

Life of this patent

Abstract

Claims19