On-chip logic accelerator
AssigneeInternational Business Machines Corporation
InventorsBulent Abali, Sameh Asaad
Life of this patent
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Abstract
Embodiments of the invention are directed to a computer-implemented method of memory acceleration. The computer-implemented method includes mapping, by a processor, an array of logic blocks in system memory to an array of logic blocks stored in level 1 (L1) on an accelerator chip, wherein each logic block stores a respective look up table for a function, wherein each function row of a respective look up table stores an output function value and a combination of inputs to the function. The processor determines that a number of instances of request for the output function value from a logic block is less than a first threshold. The processor evicts the function row to a higher level memory.
Claims9
A computer-implemented method for memory acceleration, the method comprising:
- mapping, by a processor, an array of logic blocks in system memory to an array of logic blocks stored in level 1 (L1) on an accelerator chip, wherein each logic block stores a respective look up table for a function, wherein each function row of a respective look up table stores an output function value and a combination of inputs to the function;
- determining, by the processor, that a number of instances of request for the output function value from a logic block is less than a first threshold and greater than a second threshold, wherein the second threshold is less than the first threshold;
- and
- evicting, by the processor, the function row to victim cache.
A system for memory acceleration, the system comprising:
- a processor communicatively coupled to a memory, the processor configured to:
- map an array of logic blocks in system memory to an array of logic blocks stored in level 1 (L1) on an accelerator chip, wherein each logic block stores a respective look up table for a function, wherein each function row of a respective look up table stores an output function value and a combination of inputs to the function herein each look up table stores output functions values that are based on combinations of inputs to the function;
- determine that a number of instances of request for the output functions value from a logic block is less than a first threshold and greater than a second threshold, wherein the second threshold is less than the first threshold;
- and
- evict the function row to victim cache.
A computer program product for memory acceleration, the computer product comprising a computer readable storage medium having program instructions embodied therewith, the instructions executable by a processor to cause the processor to:
- map an array of logic blocks in system memory to an array of logic blocks stored in level 1 (L1) on an accelerator chip, wherein each logic block stores a respective look up table for a function, wherein each function row of a respective look up table stores an output function value and a combination of inputs to the function;
- determine that a number of instances of request for the output function value from a logic block is less than a first threshold and greater than a second threshold, wherein the second threshold is less than the first threshold;
- and
- evict the function row to victim cache.
Dependencies are inferred from the claim text.