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US 10,884,941 B2Granted
Techniques to store data for critical chunk operations
AssigneeIntel Corporation
InventorBill Nale
Life of this patent
Estimating the term…
Abstract
Various embodiments are generally directed to techniques to store data for critical chunk operations, such as by utilizing a spare lane, for instance. Some embodiments are particularly directed to a memory controller that stores a portion of a critical chunk in a spare lane to enable the entire critical chunk to be stored in a half of the cache line.
Claims25
An apparatus for memory management, the apparatus comprising:
- a memory controller comprising logic, at least a portion of the logic implemented in circuitry coupled to memory, the logic to:
- implement a spare lane in the memory, the memory to include a cache line comprising first and second portions of a critical chunk, the first portion included in a first half of the cache line and the second portion included in a second half of the cache line;
- identify a set of bits in the spare lane that correspond to the cache line, the set of bits to comprise a first subset of bits that correspond to the first half of the cache line and a second subset of bits that correspond to the second half of the cache line;
- and
- store a copy of the first portion of the cache line to the second subset of bits in the spare lane.
2 more elements
A computer-implemented method, comprising:
- implementing a spare lane in a memory, the memory including a cache line comprising first and second portions of a critical chunk, the first portion included in a first half of the cache line and the second portion included in a second half of the cache line;
- identifying a set of bits in the spare lane that correspond to the cache line, the set of bits comprising a first subset of bits that correspond to the first half of the cache line and a second subset of bits that correspond to the second half of the cache line;
- and
- storing a copy of the first portion of the cache line to the second subset of bits in the spare lane.
1 more element
At least one non-transitory computer-readable medium comprising a set of instructions that, in response to being executed by a processor circuit, cause the processor circuit to:
- implement a spare lane in a memory, the memory to include a cache line comprising first and second portions of a critical chunk, the first portion included in a first half of the cache line and the second portion included in a second half of the cache line;
- identify a set of bits in the spare lane that correspond to the cache line, the set of bits to comprise a first subset of bits that correspond to the first half of the cache line and a second subset of bits that correspond to the second half of the cache line;
- and
- store a copy of the first portion of the cache line to the second subset of bits in the spare lane.
1 more element
Dependencies are inferred from the claim text.