Independent and separate entity-based cache
AssigneeIntel Corporation
InventorsAltug Koker, Joydeep Ray, James A. Valerio, Abhishek R. Appu, Vasanth Ranganathan
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Abstract
A mechanism is described for facilitating independent and separate entity-based graphics cache at computing devices. A method of embodiments, as described herein, includes facilitate hosting of a plurality of cache at a plurality of entities associated with a graphics processor, wherein each entity hosts at least one cache, and wherein an entity includes a dual sub-slice (DSS) or a streaming multiprocessor (SM).
Claims21
An apparatus comprising:
- one or more processors including a graphics processor to:
- facilitate hosting of a plurality of graphics caches at a plurality of entities associated with the graphics processor, wherein each entity of the plurality of entities is to host at least one graphics cache, and wherein each entity includes a plurality of cores;
- and
- map each of the plurality of graphics caches to an entire system cache or memory to cache data stored in the system cache or memory,
- wherein each graphics cache is logically independent of and separate from other graphics caches of the plurality of graphics caches, and wherein each graphics cache has a direct and independent path to a data port associated with the system cache or memory.
A method comprising:
- facilitating hosting of a plurality of graphics caches at a plurality of entities associated with a graphics processor, wherein each entity of the plurality of entities is to host at least one graphics cache, and wherein each entity includes a plurality of cores;
- and
- mapping each of the plurality of graphics caches to an entire system cache or memory to cache data stored in the system cache or memory,
- wherein each graphics cache is logically independent of and separate from other graphics caches of the plurality of graphics caches, and wherein each graphics cache has a direct and independent path to a data port associated with the system cache or memory.
At least one non-transitory machine-readable medium comprising instructions that when executed by a computing device, cause the computing device to perform operations comprising:
- facilitating hosting of a plurality of graphics caches at a plurality of entities associated with a graphics processor, wherein each entity of the plurality of entities is to host at least one graphics cache, and wherein each entity of the plurality of entities includes a plurality of cores;
- and
- mapping each of the plurality of graphics caches to an entire system cache or memory to cache data stored in the system cache or memory,
- wherein each graphics cache is logically independent of and separate from other graphics caches of the plurality of graphics caches, and wherein each graphics cache has a direct and independent path to a data port associated with the system cache or memory.
Dependencies are inferred from the claim text.