Interprocessor memory status communication

A computer program product, the computer program product comprising one or more non-transitory computer readable storage media and program instructions stored on the one or more non-transitory computer readable storage media, the program instructions comprising instructions to, in a transactional memory environment including a plurality of processors comprising a first processor and an additional processor:

• identify a first memory location and a second memory location, wherein the first memory location and the second memory location are for a transaction by the additional processor, wherein the transaction has associated therewith a read-set and a write-set, and wherein each of the read-set and the write-set comprises one or more memory locations;
• send a probe request comprising a cross-interrogate from the first processor to the additional processor, the probe request including the first memory location;
• generate an indication comprising a read bit and a write bit, by the additional processor, wherein the indication denotes a status for the first memory location, wherein the indication comprises a value of 1, and wherein the indication is selected from a group consisting of:
• the read bit and the write bit is in a state 01 denoting that the first memory location is in use for the read-set, the read bit and the write bit is in a state 10 denoting that the first memory location is in use for the write-set, and the read bit and the write bit is in a state 11 denoting that the first memory location is in use for both the read-set and the write-set;
• send the indication from the additional processor to the first processor;
• and
• proceed, by the first processor, to send another probe request including the second memory location in response to the indication comprising a value of 1.

A computer system comprising:

• one or more processing circuits;
• and
• one or more computer readable storage media;
• wherein the computer readable storage media store instructions for execution by the one or more processing circuits;
• the instructions comprising instructions to, in a transactional memory environment including a plurality of processors comprising a first processor and an additional processor:
• identify a first memory location and a second memory location, wherein the first memory location and the second memory location are for a transaction by the additional processor, wherein the transaction has associated therewith a read-set and a write-set, and wherein each of the read-set and the write-set comprises one or more memory locations;
• send a probe request comprising a cross-interrogate from the first processor to the additional processor, the probe request including the first memory location;
• generate an indication comprising a read bit and a write bit, by the additional processor, wherein the indication denotes a status for the first memory location, wherein the indication comprises a value of 1, and wherein the indication is selected from a group consisting of:
• the read bit and the write bit is in a state 01 denoting that the first memory location is in use for the read-set, the read bit and the write bit is in a state 10 denoting that the first memory location is in use for the write-set, and the read bit and the write bit is in a state 11 denoting that the first memory location is in use for both the read-set and the write-set;
• send the indication from the additional processor to the first processor;
• and
• proceed, by the first processor, to send another probe request including the second memory location in response to the indication comprising a value of 1.