Memory module with local synchronization and method of operation

A memory module configured to couple to a memory controller via one or more clock signal lines, a set of control signal lines and N sets of n-bit wide data/strobe signal lines, where N and n are integers larger than one, comprising:

• a control circuit configured to receive a system clock from the memory controller via the one or more clock signal lines, and input address and control (C/A) signals from the memory controller via the control signal lines, the control circuit being further configured to output a module clock signal, module C/A signals and data buffer control signals in response to the system clock and the input C/A signals;
• N data buffers configurable to receive the module clock signal and the data buffer control signals from the control circuit, wherein a respective data buffer of the N data buffers is configurable to operatively couple to a respective set of n-bit wide data/strobe signal lines, the respective data buffer including a n-bit wide data path and logic configured to control the data path in response to the data buffer control signals, the n-bit wide data path including at least one programmable delay element, wherein the respective data buffer is further configurable to generate a respective local clock signal in response to the module clock signal, and wherein the respective local clock signal is phase-locked with the module clock signal and has a respective programmable delay from the module clock signal;
• and
• memory devices organized in one or more ranks and including N groups of memory devices corresponding to respective ones of the N data buffers, each group of memory devices including at least one memory device in each of the one or more ranks, wherein a respective group of the N groups of memory devices is configurable to receive the module C/A signals from the control circuit and a respective local clock signal from a corresponding data buffer of the N data buffers, and wherein the respective group of the N groups of memory devices is further configurable to communicate data and data strobe signals with the memory controller via the n-bit wide data path in the corresponding data buffer and in response to the module C/A signals from the control circuit and the respective local clock signal from the corresponding data buffer.