Flash memory controller to perform delegated move to host-specified destination

An apparatus comprising instructions stored on non-transitory machine-readable media, for use in controlling flash memory, the flash memory having a hierarchical structure of subdivisions, each subdivision of the flash memory at a higher tier of the hierarchical structure comprising plural subdivisions at a lower tier of the hierarchical structure, said instructions when executed to cause circuitry of a memory controller integrated circuit to:

• receive read requests and write requests from a host and control the performance of the read requests and the write requests in the flash memory, including the storage of first data in a first subdivision at the lower tier, the first subdivision at the lower tier being associated with a first subdivision at the higher tier, in response to a first write request;
• receive one or more commands from the host to copy the data from the first subdivision at the lower tier into a second subdivision at the lower tier, and to subsequently erase the first subdivision at the lower tier, so as to place the first subdivision at the lower tier into a state in which it can be reprogrammed, wherein the second subdivision at the lower tier is associated with a second subdivision at the higher tier;
• and
• receive a host-supplied address for each of the read requests and the one or more commands, and responsively generate physical addresses to select a specific subdivision at each of the higher tier and the lower tier;
• wherein a non-exhaustive portion of each host supplied-address as sent by the host is mapped in advance to the subdivisions at the higher tier, the higher tier comprising one of a channel, a die, or a block within a die, so as to select one of the subdivisions at the higher tier;
• wherein said instructions when executed are to cause the memory controller integrated circuit to copy the first data into the storage location corresponding to the second subdivision at the lower tier without sending the data to the host, responsive to the one or more commands;
• wherein the one or more commands are to select each of the first subdivision at the higher tier and the second subdivision at the higher tier respectively as a source of the data to be copied and a destination of the data to be copied;
• and
• wherein said instructions are further to cause the memory controller integrated circuit to assign address information for a storage location in the flash memory in connection with a prior write request received from the host for the data and to transmit to the host metadata which identifies the address information, and wherein each host-supplied address for the data includes the address information.

A storage drive, comprising:

• flash memory having a hierarchical structure of subdivisions, each subdivision of the flash memory at a higher tier of the hierarchical structure comprising plural subdivisions at a lower tier of the hierarchical structure;
• and
• a memory controller integrated circuit to control flash memory, the memory controller integrated circuit comprising
• logic to receive read requests and write requests from the host and to control the performance of the read requests and the write requests in the flash memory, including the storage of first data in a first subdivision at the lower tier, the first subdivision at the lower tier being associated with a first subdivision at the higher tier, in response to a first write request,
• logic to receive one or more commands from the host to copy the data from the first subdivision at the lower tier into a second subdivision at the lower tier, and to subsequently erase the first subdivision at the lower tier, so as to place the first subdivision at the lower tier into a state in which it can be reprogrammed, wherein the second subdivision at the lower tier is associated with a second subdivision at the higher tier, and
• logic to receive a host-supplied address for each of the read requests and the one or more commands, and to responsively generate physical addresses to select a specific subdivision at each of the higher tier and the lower tier;
• wherein a non-exhaustive portion of each host supplied-address as sent by the host is mapped in advance to the subdivisions at the higher tier, the higher tier comprising one of a channel, a die, or a block within a die, such that each host-supplied address is effective to select one of the subdivisions at the higher tier according to a value of the non-exhaustive portion;
• wherein the memory controller integrated circuit is to copy the first data into the storage location corresponding to the second subdivision at the lower tier, responsive to the one or more commands, without sending the data to the host;
• wherein said memory controller integrated circuit further includes logic to assign address information for a storage location in the flash memory in connection with a prior write request received from the host for the data and to transmit to the host metadata which identifies the address information, and wherein each host-supplied address for the data includes the address information;
• and
• wherein each said logic comprises at least one of (1) hardware circuit elements or (2) instructions stored on non-transitory storage which, when executed, are to control circuitry of said memory controller integrated circuit.