Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices

A memory system comprising:

• a semiconductor memory device;
• and
• a memory controller configured to control the semiconductor memory device, and to transmit main data to the semiconductor memory device, the memory controller including a first error correction code (ECC) engine configured to generate write parity data based on the main data,
• wherein the semiconductor memory device comprises:
• a second ECC engine configured to generate parity data based on the main data received from the memory controller;
• and
• a memory cell array including a plurality of dynamic memory cells, the memory cell array including a normal cell region configured to store the main data and a parity cell region configured to selectively store either the parity data or both of the write parity data and the parity data.

A method of operating a semiconductor memory device including a memory cell array and an error correction code (ECC) engine, the memory cell array including a normal cell region and a parity cell region, the method comprising:

• receiving, in the semiconductor memory device, main data and sub data from an external memory controller, the sub data including first parity data to correct for at least one error of corresponding main data;
• by the ECC engine, generating second parity data based on the main data received at the ECC engine;
• and
• selectively storing, based on an error correction mode, in the semiconductor memory device, the second parity data and the sub data in the parity cell region while storing the main data in the normal cell region,
• wherein the sub data is stored in the parity cell region in a first error correction mode of the error correction mode, and
• wherein either the second parity data or both of the sub data and the second parity data is stored in the parity cell region in a second error correction mode of the error correction mode.