Memory device, memory system including the same and operation method of the memory system

A memory system, comprising:

• a memory controller;
• and
• a memory device,
• wherein the memory controller comprises:
• a system error correction code generating circuit suitable for generating a system error correction code to be stored in the memory device along with a write data based on the write data;
• and
• a system error correction circuit suitable for correcting an error of data which is read from the memory device, based on the system error correction code which is read from the memory device,
• wherein the memory controller commands the memory device to perform a read retry operation when an error correction operation of the system error correction circuit fails, and
• wherein the memory device comprises:
• an in-memory error correction code generating circuit suitable for generating an in-memory error correction code based on the write data and the system error correction code that are received in a write operation;
• a memory core suitable for storing the write data, the system error correction code, and the in-memory error correction code;
• an in-memory error correction circuit suitable for correcting, in a read operation, an error of the data and the system error correction code which are read from the memory core, based on the in-memory error correction code which is read from the memory core;
• a data transmitter suitable for transmitting, in the read operation, the data and the system error correction code whose errors are corrected by the in-memory error correction circuit to the memory controller;
• an error correction history storing circuit suitable for storing an error correction history of the in-memory error correction circuit;
• and
• a read retry control circuit suitable for comparing, in a read retry operation, an address stored in the error correction history storing circuit with a read retry address, and when the address and the read retry address are the same, controlling the data and the system error correction code that are read from the memory core based on the read retry address, to be transmitted to the memory controller through the data transmitter without error correction.

A method for operating a memory system including a memory device and a memory controller, the method comprising:

• reading, by the memory device, a data, a system error correction code, and an in-memory error correction code which are stored in the memory device, based on a read command and a read address transferred from the memory controller;
• correcting, by the memory device, an error of the read data and the read system error correction code based on the read in-memory error correction code;
• storing, by the memory device, the read address as an error correction address when the error is corrected in the correcting of the error;
• transmitting, by the memory device, the error-corrected data and system error correction code to the memory controller;
• correcting, by the memory controller, an error of the error-corrected data transmitted from the memory device, based on the error-corrected system error correction code transmitted from the memory device;
• transferring, by the memory controller, a read retry command and a read retry address to the memory device when a failure occurs in the correcting of the error of the error-corrected data;
• reading, by the memory device, the data, the system error correction code, and the in-memory error correction code which are stored in the memory device, based on the read retry address and the read retry command;
• comparing the read retry address with the error correction address;
• when the read retry address and the error correction address are the same in the comparing, transmitting, by the memory device, the data and the system error correction code that are read based on the read retry address and the read retry command to the memory controller without error correction;
• and
• correcting, by the memory controller, an error of the data transmitted from the memory device, based on the system error correction code transmitted from the memory device.

A memory device, comprising:

• an in-memory error correction code generating circuit suitable for generating, in a write operation, an in-memory error correction code based on data and a system error correction code provide by a memory controller;
• a memory core suitable for storing the data, the system error correction code, and the in-memory error correction code;
• and
• an in-memory error correction circuit suitable for correcting, in a read operation, an error of the data and the system error correction code which are read from the memory core, based on the in-memory error correction code read from the memory core,
• wherein the error-corrected data and system error correction code are provided to a memory controller in the read operation, and when a read retry operation is performed on a same address as the error-corrected data, the data and the system error correction code bypassed by the in-memory error correction circuit or error correction bit information, are provided to the memory controller.