Fast parallel CRC determination to support SSD testing

An automated test environment (ATE) system used for testing solid state drives (SSDs), said system comprising:

• a test data pattern generator for generating test data at a rate of at least 8 Gbytes per second for storage onto an SSD under test (DUT), wherein the test data comprises a respective N bit word generated every clock cycle and comprising a plurality of 8 subwords;
• a pipelined digest circuit operable to employ a digest function on each N bit word to produce a respective word digest value for each N bit word every clock cycle;
• and
• a storage circuit operable to store each N bit word along with an associated word digest value to the DUT and wherein the pipelined digest circuit comprises:
• a plurality of first circuits each operable to perform a first digest function on a respective subword of the plurality of subwords, in parallel, to produce a plurality of subword digests wherein each first circuit operates within a first clock cycle and performs a function that is equivalent to shifting a respective subword through an LFSR having zero start state;
• a plurality of second circuits each operable, within a second clock cycle, to perform a second digest function on a respective subword digest of the plurality of subword digests, the second digest function being equivalent to shifting said respective subword digest through the LFSR then followed by (I×M) zero bits, wherein I is related to a word position, within the N bit word, of a respective subword that generated the respective subword digest;
• and
• an XOR circuit operable to XOR outputs of said plurality of second circuits together along with a shifted prior LFSR state to produce the word digest of said N bit data word.

A method of testing memory storage devices, said method comprising:

• generating test data for storage onto a memory storage device under test (DUT) using a test data pattern generator, wherein the generating produces a respective N bit word every clock cycle and wherein the N bit word comprises a plurality of subwords;
• performing a digest function on each N bit word to produce, every clock cycle, a respective word digest for each N bit word using a digest circuit;
• storing each N bit word along with an associated word digest to the DUT using a storage circuit, wherein the digest circuit operates by:
• using a plurality of first circuits each to perform a first digest function on a respective subword of the plurality of subwords, in parallel, to produce a plurality of subword digests wherein each first circuit operates within a single clock cycle to perform a function that is equivalent to shifting a respective subword through a linear feedback shift register (LFSR) having zero start state;
• using a plurality of second circuits, within a single clock cycle, to each perform a second digest function on a respective subword digest of the plurality of subword digests, the second digest function being equivalent to shifting said respective subword digest through the LFSR then followed by (I×M) zero bits, wherein I is related to a word position, within the N bit word, of a respective subword that generated the respective subword digest;
• and
• XORing outputs of said plurality of second circuits together along with a shifted prior LFSR state to produce the word digest of said N bit data word;
• reading an N bit word and associated word digest from the DUT;
• verifying that said N bit word is accurately stored on said DUT by analyzing said N bit word and said associated word digest;
• and
• recording a result of said verifying.