Method and apparatus for multithreaded data transmission in a tee system

A non-transitory, computer-readable medium storing one or more instructions executable by one or more processors serving for a thread in a plurality of threads on a non-trusted execution environment (TEE) side in a TEE system, wherein:

• the TEE system comprises a TEE side and the non-TEE side,
• the non-TEE side comprises a shared memory, the shared memory comprises a first address, a second address, and a plurality of consecutive third addresses, wherein the first address stores a write offset address, the write offset address indicates a writeable start address in the plurality of consecutive third addresses, the second address stores a read offset address, the read offset address indicates a readable start address in the plurality of consecutive third addresses, the plurality of consecutive third addresses store data from the TEE side,
• the non-TEE side is preconfigured with a non-TEE side thread lock corresponding to the shared memory,
• the non-TEE side comprises the one or more processors, and
• the one or more instructions, when executed by the one or more processors, perform one or more operations comprising:
• obtaining the non-TEE side thread lock;
• obtaining the write offset address and the read offset address respectively by reading the first address and the second address;
• reading unread bytes in written data in the plurality of consecutive third addresses as second data, wherein the unread bytes are determined based on the write offset address and the read offset address, and each address corresponds to one byte;
• updating the read offset address in the second address;
• and
• releasing the non-TEE side thread lock.

A computer-implemented system for data transmission in a trusted execution environment (TEE) system, wherein:

• the TEE system comprises a TEE side and a non-TEE side,
• the non-TEE side comprises a shared memory, the shared memory comprises a first address, a second address, and a plurality of consecutive third addresses, wherein the first address stores a write offset address, the write offset address indicates a writeable start address in the plurality of consecutive third addresses, the second address stores a read offset address, the read offset address indicates a readable start address in the plurality of consecutive third addresses, the plurality of consecutive third addresses store data from the TEE side,
• the non-TEE side is preconfigured with a non-TEE side thread lock corresponding to the shared memory,
• the non-TEE side comprises one or more processors serving for a thread on the non-TEE side, and one or more computer memory devices interoperably coupled with the one or more processors and having tangible, non-transitory, machine-readable media storing one or more instructions that, when executed by the one or more processors, perform one or more operations comprising:
• obtaining the non-TEE side thread lock;
• obtaining the write offset address and the read offset address respectively by reading the first address and the second address;
• reading unread bytes in written data in the plurality of consecutive third addresses as second data, wherein the unread bytes are determined based on the write offset address and the read offset address, and each address corresponds to one byte;
• updating the read offset address in the second address;
• and
• releasing the non-TEE side thread lock.