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AssigneeApple Inc.
InventorsJeremy C. Andrus, John G. Dorsey, James M. Magee, Daniel A. Chimene, Cyril de la Cropte de Chanterac, Bryan R. Hinch, Aditya Venkataraman, Andrei Dorofeev, Nigel R. Gamble, Russell A. Blaine, Constantin Pistol
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Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
A computer-implemented method, performed on a system comprising an asymmetric multi-core processor having a plurality of cores of at least two different core types, the method comprising:
A computer-implemented method, performed on a system comprising an asymmetric multi-core processor having a plurality of cores of at least two different core types, the method comprising:
A non-transitory computer-readable medium having executable instructions stored thereon, that when executed by a processing system comprising at least one hardware processor coupled to a memory perform operations, the operations comprising:
A non-transitory computer-readable medium having executable instructions stored thereon, that when executed by a processing system comprising at least one hardware processor coupled to a memory perform operations, the operations comprising:
A system comprising at least one hardware processor coupled to a memory programmed with executable instructions that, when executed by the at least one hardware processor perform operations, the operations comprising:
A system comprising at least one hardware processor coupled to a memory programmed with executable instructions that, when executed by the at least one hardware processor perform operations, the operations comprising:
Dependencies are inferred from the claim text.