Scheduling tasks using targeted pipelines
AssigneeImagination Technologies Limited
InventorsSimon Nield, Yoong-Chert Foo, Adam de Grasse, Luca Iuliano
Life of this patent
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Abstract
A method of scheduling instructions within a parallel processing unit is described. The method comprises decoding, in an instruction decoder, an instruction in a scheduled task in an active state, and checking, by an instruction controller, if an ALU targeted by the decoded instruction is a primary instruction pipeline. If the targeted ALU is a primary instruction pipeline, a list associated with the primary instruction pipeline is checked to determine whether the scheduled task is already included in the list. If the scheduled task is already included in the list, the decoded instruction is sent to the primary instruction pipeline.
Claims13
A method of scheduling instructions within a parallel processing unit comprising:
- decoding, in an instruction decoder, an instruction in a scheduled task in an active state;
- checking, by an instruction controller, if an ALU targeted by the decoded instruction is a primary instruction pipeline;
- in response to determining that the ALU targeted by the decoded instruction is a primary instruction pipeline, checking a list associated with the primary instruction pipeline to determine whether the scheduled task is already included in the list, wherein the list associated with the primary instruction pipeline identifies scheduled tasks currently active in the primary instruction pipeline;
- and
- in response to determining that the scheduled task is already included in the list, sending the decoded instruction to the primary instruction pipeline.
An instruction controller comprising:
- an input for receiving an instruction in a scheduled task in an active state from a scheduler;
- an instruction decoder arranged to decode the received instruction;
- a memory element arranged to store a list of scheduled tasks associated with a primary instruction pipeline in a parallel processing unit, wherein the list associated with the primary instruction pipeline identifies scheduled tasks currently active on the primary instruction pipeline;
- and
- hardware logic arranged to check if an ALU targeted by the decoded instruction is the primary instruction pipeline and in response to determining that the ALU targeted by the decoded instruction is a primary instruction pipeline, to check the list associated with the primary instruction pipeline to determine whether the scheduled task is already included in the list and in response to determining that the scheduled task is already included in the list, to send the decoded instruction to the primary instruction pipeline.
A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an instruction controller, the instruction controller comprising:
- an input for receiving an instruction in a scheduled task in an active state from a scheduler;
- an instruction decoder arranged to decode the received instruction;
- a memory element arranged to store a list of scheduled tasks associated with a primary instruction pipeline in a parallel processing unit, wherein the list associated with the primary instruction pipeline identifies scheduled tasks currently active on the primary instruction pipeline;
- and
- hardware logic arranged to check if an ALU targeted by the decoded instruction is the primary instruction pipeline and in response to determining that the ALU targeted by the decoded instruction is a primary instruction pipeline, to check the list associated with the primary instruction pipeline to determine whether the scheduled task is already included in the list and in response to determining that the scheduled task is already included in the list, to send the decoded instruction to the primary instruction pipeline.
Dependencies are inferred from the claim text.