System and method for variable lane architecture
AssigneeFuturewei Technologies, Inc.
InventorsSushma Wokhlu, Alan Gatherer, Ashish Rai Shrivastava
Life of this patent
Estimating the term…
Abstract
A system and method for variable lane architecture includes memory blocks located in a memory bank, one or more computing nodes forming a vector instruction pipeline for executing a task, each of the computing nodes located in the memory bank, each of the computing nodes executing a portion of the task independently of other ones of the computing nodes, and a global program controller unit (GPCU) forming a scalar instruction pipeline for executing the task, the GPCU configured to schedule instructions for the task at one or more of the computing nodes, the GPCU further configured to dispatch an address for the memory blocks used by each of the computing nodes to the computing nodes.
Claims22
A processing system, comprising:
- a plurality of computing nodes forming a plurality of vector instruction pipelines, the plurality of vector instruction pipelines comprising parallel processing lanes for execution of a task comprising instructions;
- and
- a global program controller unit (GPCU) coupled to and controlling the plurality of computing nodes during execution of the task, the GPCU:
- receiving beat signals from each computing node, each beat signal including a beat, and adding the received beats to counters of a plurality of counters that each correspond to the plurality of computing nodes, each computing node generating a beat signal upon completion of an instruction, and the GPCU maintaining a beat count for the each computing node;
- comparing the plurality of counters;
- determining a fastest computing node and a slowest computing node;
- and
- moderating one or both of an instruction flow or a data flow to the fastest computing node when a fastest computing node beat count exceeds a difference threshold from the slowest computing node beat count, the GPCU operating individual computing nodes asynchronously while maintaining beat counts of all computing nodes within a beat difference range.
A processing method in a global program controller unit (GPCU) coupled to and controlling a plurality of computing nodes during execution of a task comprising instructions, the plurality of computing nodes forming a plurality of vector instruction pipelines, the plurality of vector instruction pipelines comprising parallel processing lanes for execution of the task, the method comprising:
- the GPCU receiving beat signals from each computing node, each beat signal including a beat, and adding the received beats to counters of a plurality of counters that each correspond to the plurality of computing nodes, each computing node generating a beat signal upon completion of an instruction, and the GPCU maintaining a beat count for the each computing node;
- the GPCU comparing the plurality of counters;
- the GPCU determining a fastest computing node and a slowest computing node;
- and
- the GPCU moderating one or both of an instruction flow or a data flow to the fastest computing node when a fastest computing node beat count exceeds a difference threshold from the slowest computing node beat count, the GPCU operating individual computing nodes asynchronously while maintaining beat counts of all computing nodes within a beat difference range.
Dependencies are inferred from the claim text.