Synchronized access to data in shared memory by resolving conflicting accesses by co-located hardware threads

A method of data processing in a processing unit of a data processing system, the processing unit including a processor core and a cache memory, said method comprising:

• an execution unit of the processor core executing instructions in a plurality of concurrent hardware threads of execution including at least first and second hardware threads, wherein the executing includes executing, within the first hardware thread, a first load-reserve instruction that identifies a target address for which a reservation is requested;
• a load unit of the processor core recording, within the processor core, the target address of the first load-reserve instruction;
• and
• the load unit detecting in the second hardware thread a second load-reserve instruction identifying the target address recorded within the processor core by the load unit and, based on detecting the second load-reserve instruction, blocking the second load-reserve instruction from establishing a reservation for the target address in reservation logic of the cache memory.

A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• a processing unit, including:
• a cache memory including reservation logic;
• and
• a processor core coupled to the cache memory, the processor core comprising:
• an execution unit that executes instructions in a plurality of concurrent hardware threads of execution including at least first and second hardware threads, wherein the instructions include, within the first hardware thread, a first load-reserve instruction that identifies a target address for which a reservation is requested;
• and
• a load unit that records, within the processor core, the target address of the first load-reserve instruction, detects, in the second hardware thread, a second load-reserve instruction identifying the target address recorded by the load unit, and based on detection of the second load-reserve instruction, blocks the second load-reserve instruction from establishing a reservation for the target address in the reservation logic of the cache memory.