Arithmetic processing device and method of controlling arithmetic processing device

A method of controlling an arithmetic processing device including a load store queue that stores load or store instructions with an upper limit being a first number, and sequentially outputs the stored load or store instructions to cause a cache or a memory to execute processing of data in accordance with the output load or store instructions, the control method comprising:

• controlling an instruction management circuit to acquire the load or store instructions;
• determining a queued number of load or store instructions which have not been output from the load or store queue among load store instructions output from the instruction management circuit, by using a first signal indicating an output of the load store queue and a second signal indicating an output of the instruction management circuit;
• controlling, when the queued number is smaller than a second number which is larger than the first number, the instruction management circuit to allocate a provisional number to each of the load or store instructions and to output the acquired load or store instructions to which the provisional number allocated;
• controlling a storage management circuit to acquire the load or store instructions output from the instruction management circuit;
• and
• controlling, when a stored number of load or store instructions stored in the load or store queue is smaller than the first number, the storage management circuit to allocate an actual number acquired based on the provisional number to each of the acquired load or store instructions and to store the load or store instructions acquired by the storage management circuit in the load store queue in accordance with the actual number.