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US 10,884,735 B2Granted
Instruction and logic for predication and implicit destination
AssigneeIntel Corporation
InventorsJayesh Iyer, Jamison Collins, Sebastian Winkel, Howard Chen
Life of this patent
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Abstract
A processor includes a front end to receive an instruction. The processor also includes a core to execute the instruction. The core includes logic to execute a base function of the instruction to yield a result, generate a predicate value of a comparison of the result based upon a predication setting in the instruction, and set the predicate value in a register. The processor also includes a retirement unit to retire the instruction.
Claims20
A processor, comprising:
- a set of registers designated to store predicate values;
- a decoder to decode a single first instruction, an opcode of the single first instruction to indicate a generation of a predicate value and a result;
- execution circuitry to execute the decoded single first instruction according to the opcode to:
- execute a base function of the instruction to generate and store a primary result,
- generate a predicate value as a secondary result of execution of the instruction, wherein the predicate value is generated in association with generation of the primary result, and
- set the predicate value in one of the registers of the set of registers;
- and
- a retirement unit to retire the executed single first instruction.
5 more elements
A method comprising:
- decoding a single first instruction, an opcode of the single first instruction to indicate a generation of a predicate value and a result;
- executing the decoded single first instruction according to the opcode to:
- perform a base function to generate a primary result and a secondary result, wherein the secondary result comprises a predicate value associated with the primary result, and
- set the predicate value in a particular one of the set of registers;
- and
- retiring the particular instruction.
3 more elements
A system comprising:
- memory to at least store a single first instruction;
- and
- a processor comprising:
- a set of registers designated to store predicate values;
- a decoder to decode the single first instruction, an opcode of the instruction to indicate a generation of a predicate value and a result;
- execution circuitry to execute the decoded single instruction according to the opcode to:
- execute a base function of the instruction to generate and store a primary result,
- generate a predicate value as a secondary result of execution of the instruction, wherein the predicate value is generated in association with generation of the primary result, and
- set the predicate value in one of the registers of the set of registers;
- and
- a retirement unit to retire the executed single first instruction.
8 more elements
Dependencies are inferred from the claim text.