Memory ordering annotations for binary emulation

A computer system comprising:

• one or more processors;
• and one or more computer-readable media having stored thereon computer-executable instructions that are executable by the one or more processors to cause the computer system to generate binary emulation metadata during source code compilation, including at least:
• during compilation of source code into a plurality of first machine code instructions of a first processor Instruction Set Architecture (ISA), encountering a memory ordering constraint specified in the source code;
• based on encountering the memory ordering constraint, generating, during the compilation, binary emulation metadata that is configured to be used during emulation of one or more of the plurality of first machine code instructions on a second processor ISA to enforce the memory ordering constraint within one or more corresponding second machine code instructions of the second processor ISA, wherein the generated binary emulation metadata includes a memory ordering data structure that associates a corresponding instruction memory address of each of the one or more of the plurality of first machine code instructions with at least one of a read barrier or a write barrier;
• and
• storing the generated binary emulation metadata in association with the plurality of first machine code instructions, including storing the memory ordering data structure separate from an instruction stream comprising the plurality of first machine code instructions.

A hardware storage device having stored thereon computer-executable instructions that are executable by one or more processors to cause a computer system to generate binary emulation metadata during source code compilation, including at least:

• during compilation of source code into a plurality of first machine code instructions of a first processor Instruction Set Architecture (ISA), encountering a memory ordering constraint specified in the source code;
• based on encountering the memory ordering constraint,
• generating, during the compilation, binary emulation metadata that is configured to be used during emulation of one or more of the plurality of first machine code instructions on a second processor ISA to enforce the memory ordering constraint within one or more corresponding second machine code instructions of the second processor ISA, wherein the generated binary emulation metadata includes a memory ordering data structure that associates a corresponding instruction memory address of each of the one or more of the plurality of first machine code instructions with at least one of a read barrier or a write barrier;
• and
• storing the generated binary emulation metadata in association with the plurality of first machine code instructions, including storing the memory ordering data structure separate from an instruction stream comprising the plurality of first machine code instructions.