Back to results
US 10,884,674 B2Granted
Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorsYousuke Hagiwara, Kenta Shibasaki, Yumi Takada
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a semiconductor memory device includes a memory cell array, first to third circuits. The first circuit is configured to control duty cycles of first and second signals based on a third signal, and output fourth and fifth signals. The second circuit is configured to acquire information regarding duty cycles. The third circuit is configured to control the third signal. The second circuit includes a switching circuit and a comparator. The switching circuit is configured to transfer the fourth and fifth signals to first and second nodes. The comparator is configured to compare a signal voltages in the first and second nodes, and output the comparison result to the third circuit.
Claims20
A semiconductor memory device, comprising:
- a memory cell array configured to hold data;
- a first circuit configured to, when outputting data read from the memory cell array to an external device, receive a first signal and a second signal from the external device, control duty cycles of the first signal and the second signal based on a third signal, and output a fourth signal and a fifth signal to the external device;
- a second circuit configured to acquire information regarding duty cycles of the fourth signal and the fifth signal;
- and
- a third circuit configured to control the third signal based on the information acquired by the second circuit,
- wherein the second circuit includes:
- a switching circuit configured to transfer the fourth signal to a first node, and the fifth signal to a second node, or transfer the fourth signal to the second node, and the fifth signal to the first node based on a sixth signal;
- and
- a comparator configured to compare a signal voltage in the first node and a signal voltage in the second node, and output the comparison result to the third circuit as the information.
6 more elements
A semiconductor memory device, comprising:
- a memory cell array configured to hold data;
- a first circuit configured to output data read from the memory cell array to an external device, receive a signal from the external device, and adjust an output impedance and a termination resistance;
- a second circuit configured to adjust an output impedance;
- a third circuit configured to acquire information for controlling the output impedance of the second circuit;
- and
- a fourth circuit configured to control the output impedance or the termination resistance of the first circuit and the output impedance of the second circuit based on the information acquired by the third circuit,
- wherein the second circuit includes:
- a first pull-up circuit that pulls up a signal voltage of a first signal in a first node to which a resistance element is connected, and changes an output impedance based on a second signal;
- a second pull-up circuit that pulls up a signal voltage of a third signal in a second node, and changes an output impedance based on a fourth signal;
- and
- a pull-down circuit that pulls down a signal voltage of the third signal in the second node, and changes an output impedance based on a fifth signal, and
- wherein the third circuit includes:
- a first switching circuit configured to transfer the first signal to a third node, and a seventh signal to a fourth node, or transfer the first signal to the fourth node, and the seventh signal to the third node based on a sixth signal;
- a first comparator configured to compare a signal voltage in the third node and a signal voltage in the fourth node, and output the comparison result to the fourth circuit;
- a second switching circuit configured to transfer the third signal to a fifth node, and an eighth signal to a sixth node, or transfer the third signal to the sixth node, and the eighth signal to the fifth node based on the sixth signal;
- and
- a second comparator configured to compare a signal voltage in the fifth node and a signal voltage in the sixth node, and output the comparison result to the fourth circuit.
14 more elements
A semiconductor memory device, comprising:
- a memory cell array configured to hold data;
- a first circuit configured to output data read from the memory cell array to an external device, receive a signal from the external device, and adjust an output impedance and a termination resistance;
- a second circuit configured to adjust an output impedance;
- a third circuit configured to acquire information for controlling the output impedance of the second circuit;
- and
- a fourth circuit configured to control the output impedance or the termination resistance of the first circuit and the output impedance of the second circuit based on the information acquired by the third circuit,
- wherein the second circuit includes:
- a first pull-up circuit that pulls up a signal voltage of a first signal in a first node to which a resistance element is connected, and changes an output impedance based on a second signal;
- a second pull-up circuit that pulls up a signal voltage of a third signal in a second node, and changes an output impedance based on a fourth signal;
- and
- a pull-down circuit that pulls down a signal voltage of the third signal in the second node, and changes an output impedance based on a fifth signal, and
- wherein the third circuit includes:
- a selection circuit configured to transfer one of the first signal or the third signal to a third node based on a sixth signal;
- a first switching circuit configured to transfer a signal of the third node to a fourth node, and an eighth signal to a fifth node, or transfer a signal of the third node to the fifth node, and the eighth signal to the fourth node based on a seventh signal;
- and
- a first comparator configured to compare a signal voltage in the fourth node and a signal voltage in the fifth node, and output the comparison result to the fourth circuit.
13 more elements
Dependencies are inferred from the claim text.