Executable memory cell
AssigneeWestern Digital Technologies, Inc.
InventorsViacheslav Dubeyko, Luis Vitorio Cargnini
Life of this patent
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Abstract
A memory system includes a memory having a first executable memory cell and a compilation unit. The compilation unit is configured to receive a sequence of instructions from a host device, convert each of the sequence of instructions into an execution stream, load a first code from the execution stream into a code portion of the first executable memory cell and load a first data from the execution stream into a data portion of the first executable memory cell. The first executable memory cell is configured to apply the first code to the first data via an arithmetic and logic unit of the first executable memory cell.
Claims20
A memory system comprising:
- a memory comprising a first executable memory cell;
- and
- a compilation unit configured to:
- receive a sequence of instructions from a host device;
- convert the sequence of instructions into an execution stream comprising a continuous stream of code and data;
- load a first code from the execution stream into a code portion of the first executable memory cell;
- and
- load a first data from the execution stream into a data portion of the first executable memory cell;
- wherein the first executable memory cell is configured to apply the first code to the first data via an arithmetic and logic unit of the first executable memory cell.
A memory system comprising:
- a memory comprising a first executable memory cell;
- and
- a compilation unit configured to:
- create a code stream from a sequence of instructions, wherein the code stream comprises a plurality of code cells, each of the plurality of code cells storing a sub-code;
- create a data stream from the sequence of instructions for storing a first operand and a second operand;
- load a first sub-code into the first executable memory cell, wherein the first sub-code is stored in a first code cell of the plurality of code cells;
- load the first operand into the first executable memory cell;
- and
- shift the first sub-code from the first code cell to a second code cell of the plurality of code cells.
A non-transitory computer-readable media including computer-executable instructions embodied thereon that, when executed by a processor, cause the processor to perform a process comprising:
- receiving a sequence of instructions;
- converting the sequence of instructions to create an execution stream comprising a continuous stream of code and data;
- loading a first code from the execution stream into a code portion of a first executable memory cell;
- loading a first data from the execution stream into a data portion of the first executable memory cell;
- and
- applying the first code to the first data via an arithmetic and logic unit of the first executable memory cell.
Dependencies are inferred from the claim text.