Command queuing
AssigneeMicron Technology, Inc.
InventorsVictor Y. Tsai, Danilo Caraccio, Daniele Balluchi, Neal A. Galbo, Robert Warren
Life of this patent
Estimating the term…
Abstract
The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.
Claims19
A method for command queuing, comprising:
- receiving a command at a memory system from a host, wherein the command includes a command descriptor block;
- placing, in response to receiving the command descriptor block, the command described by the command descriptor block in a command queue of the memory system, wherein the command received from the host on a command line is added to the command queue of the memory system while a different command that was previously received from the host and added to the command queue is concurrently being executed in the memory system on a data bus;
- changing the memory system from a Receiving Data state to a Transfer state in response to receiving, from the host, data corresponding to a receive data command;
- and
- changing the memory system from a Sending Data state to the Transfer state in response to transferring, to the host, data corresponding to a send data command from the host, wherein a queue busy bit sent from the memory system to the host while the memory system is in the Transfer state indicates whether the memory system is ready to receive commands from the host.
An apparatus, comprising:
- a controller;
- and
- a memory device coupled to the controller, wherein the apparatus is configured to:
- place a command in a command queue in response to receiving the command that includes a command descriptor block, wherein the command received from a host on a command line is added to the command queue of a memory system while a different command that was previously received from the host and added to the command queue is concurrently being executed in the memory system on a data bus;
- execute the command in response to receiving a ready to transfer command;
- change the memory system from a Receiving Data state to a Transfer state in response to receiving, from the host, data corresponding to a receive data command;
- and
- change the memory system from a Sending Data state to the Transfer state in response to transferring, to the host, data corresponding to a send data command from the host, wherein a queue busy bit sent from the memory system to the host while the memory system is in the Transfer state indicates whether the memory system is ready to receive commands from the host.
A method for command queuing, comprising:
- receiving a first command at a memory system from a host on a command line, wherein the first command includes a first command descriptor block;
- placing, in response to receiving the first command descriptor block, the first command in a command queue of the memory system;
- executing the first command in response to receiving a ready to transfer command;
- receiving a second command at the memory system from the host on the command line, wherein the second command includes a second command descriptor block;
- placing, in response to receiving the second command descriptor block, the second command in the command queue of the memory system while concurrently executing the first command on a data bus;
- changing the memory system from a Receiving Data state to a Transfer state in response to receiving, from the host, data corresponding to a receive data command;
- and
- changing the memory system from a Sending Data state to the Transfer state in response to transferring, to the host, data corresponding to a send data command from the host, wherein a queue busy bit sent from the memory system to the host while the memory system is in the Transfer state indicates whether the memory system is ready to receive commands from the host.
Dependencies are inferred from the claim text.