Host timeout avoidance in a memory device
AssigneeMicron Technology, Inc.
InventorsNadav Grosz, David Aaron Palmer
Life of this patent
Estimating the term…
Abstract
Devices and techniques for host timeout avoidance in a memory device are disclosed herein. A memory device command is received with a memory device from a host. A determination is made, with the memory device, of a host timeout interval associated with the received memory device command. A timer of the memory device is initialized to monitor a time interval from receipt of the memory device command. After partially performing the memory device command, a response to the host before the memory device timer interval reaches the host timeout interval is generated by the memory device.
Claims12
A method of preventing host reset commands of a memory device, the method comprising:
- using one or more processors of a memory device to perform operations comprising:
- receiving, a multi-block read command from a host device, the multi-block read command requesting that the memory device read multiple blocks of a memory array of a memory device;
- determining a host timeout value associated with the received multi-block read command, the host timeout value being a maximum amount of time the host device waits for completion of the multi-block read command prior to sending a host reset command to the memory device, the host timeout value identified by the memory device based upon a time between receipt of a past multi-block read command and receipt of a host reset message;
- initializing a timer of the memory device to monitor a time interval from receipt of the multi-block read command;
- causing the multi-block read command to be executed;
- determining that the timer either has expired or is within a predetermined time before expiry and the multi-block read command has not finished executing;
- and
- responsive to determining that the timer either has expired or is within a predetermined time before expiry, and that the multi-block read command has not finished executing:
- obtaining from a page buffer, data from a set of blocks already read from the memory array, the set of blocks less than a complete set of blocks specified in the multi-block read command;
- and
- causing transmission of a response to the multi-block read command to the host device, wherein the response includes the data from the set of blocks already read from the memory array.
A memory system, comprising:
- control circuitry configured to perform operations comprising:
- receiving, a multi-block read command from a host device, the multi-block read command requesting that the memory system read multiple blocks of a memory array of a memory device;
- determining a host timeout value associated with the received multi-block read command, the host timeout value being a maximum amount of time the host device waits for completion of the multi-block read command prior to sending a host reset command to the memory device, the host timeout value identified by the memory device based upon a time between receipt of a past multi-block read command and receipt of a host reset message;
- initializing a timer of the memory device to monitor a time interval from receipt of the multi-block read command;
- causing the multi-block read command to be executed;
- determining that the timer either has expired or is within a predetermined time before expiry and the multi-block read command has not finished executing;
- and
- responsive to determining that the timer either has expired or is within a predetermined time before expiry, and that the multi-block read command has not finished executing:
- obtaining from a page buffer, data from a set of blocks already read from the memory array, the set of blocks less than a complete set of blocks specified in the multi-block read command;
- and
- causing transmission of a response to the multi-block read command to the host device, wherein the response includes the data from the set of blocks already read from the memory array.
Dependencies are inferred from the claim text.