Set technique for phase change memory
AssigneeIntel Corporation
InventorsKoushik Banerjee, Lu Liu, Sanjay Rangan, Enrico Varesi, Innocenzo Tortorelli, Hongmei Wang, Mattia Boniardi
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AssigneeIntel Corporation
InventorsKoushik Banerjee, Lu Liu, Sanjay Rangan, Enrico Varesi, Innocenzo Tortorelli, Hongmei Wang, Mattia Boniardi
Estimating the term…
One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.
An apparatus comprising:
A method comprising:
A system comprising:
Dependencies are inferred from the claim text.