Providing single data rate (SDR) mode or double data rate (DDR) mode for the command and address (CA) bus of registering clock drive (RCD) for dynamic random access memory (DRAM)

An apparatus for providing a single data rate (SDR) mode or a double data rate (DDR) mode to a Registering Clock Drive (RCD) for a memory, the apparatus comprising:

• a memory controller, wherein the memory controller determines one or more data rate mode selection criteria, selects a data rate mode for a command/address (CA) bus based on the one or more data rate mode selection criteria, configures a host interface for the data rate mode and configures an RCD input interface for the data rate mode, wherein the one or more data rate mode selection criteria include one of an access statistic or a data traffic characteristic quantified using an address correlation metric;
• a clock generator coupled to the memory controller, wherein the clock generator activates a clock signal on the host interface and on the RCD input interface;
• and
• a host coupled to the memory controller, wherein the host transfers data between the host interface and the RCD input interface using the clock signal.

An apparatus for providing a single data rate (SDR) mode or a double data rate (DDR) mode to a Registering Clock Drive (RCD) for a memory, comprising:

• means for determining one or more data rate mode selection criteria;
• means for selecting a data rate mode for a command/address (CA) bus based on the one or more data rate mode selection criteria, wherein the one or more data rate mode selection criteria include one of an access statistic or a data traffic characteristic quantified using an address correlation metric;
• means for configuring a host interface for the data rate mode;
• and
• means for configuring an RCD input interface of the Registering Clock Drive (RCD) for the data rate mode.

A computer-readable medium storing computer executable code, operable on a device comprising at least one processor and at least one memory coupled to the at least one processor, wherein the at least one processor is configured to provide a single data rate (SDR) mode or a double data rate (DDR) mode to a Registering Clock Drive (RCD) for a memory, the computer executable code comprising:

• instructions for causing a computer to determine one or more data rate mode selection criteria;
• instructions for causing the computer to select a data rate mode for a command/address (CA) bus based on the one or more data rate mode selection criteria wherein the one or more data rate mode selection criteria include one of an access statistic or a data traffic characteristic quantified using an address correlation metric;
• instructions for causing the computer to configure a host interface for the data rate mode;
• and
• instructions for causing the computer to configure an RCD input interface of the Registering Clock Drive (RCD) for the data rate mode.