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US 10,884,465 B2Granted
Memory controller with processor for generating interface adjustment signals
AssigneeRambus Inc.
InventorStephen G. Tell
Life of this patent
Estimating the term…
Abstract
Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.
Claims19
A circuit comprising:
- one or more processors to generate opcodes;
- a plurality of interface control circuits, wherein each of the plurality of interface control circuits includes a respective processing element responsive to the opcodes generated by the one or more processors, wherein each interface control circuit of the plurality of interface control circuits corresponds to a respective link of a plurality of links of a device-to-device interface (DDI), and each link of the plurality of links of the DDI is for transmitting or receiving signals from one or more sources or one or more destinations external to the circuit;
- and
- a bus coupling the plurality of interface control circuits with the one or more processors to provide the opcodes generated by the one or more processors to the plurality of interface control circuits;
- wherein
- each respective interface control circuit of the plurality of interface control circuits is operable to generate one or more interface adjustment signals, in response to one or more opcodes transmitted by the one or more processors, based on the results of operations performed by the respective processing elements, for altering one or more characteristics of one or more signals coupled to the respective interface control circuit;
- and
- each of the plurality of interface control circuits controls one or more timing and/or voltage characteristics of one or more signals carried by a respective link of the DDI.
5 more elements
A method, comprising:
- generating, using one or more processors, one or more opcodes to control one or more timing and/or voltage characteristics of signals carried by a plurality of links of a device-to-device interface (DDI);
- transmitting, to a plurality of interface control circuits, the one or more opcodes, wherein each interface control circuit of the plurality of interface control circuits corresponds to a respective link of the plurality of links of the DDI;
- at each respective interface control circuit of the plurality of interface control circuits:
- generating, one or more interface adjustment signals in response to the one or more opcodes transmitted by the one or more processors;
- and
- altering, using the one or more interface adjustment signals, one or more characteristics of one or more signals coupled to the respective interface control circuit;
- where each of the plurality of interface control circuits controls one or more timing and/or voltage characteristics of one or more signals carried by a respective link of the DDI.
4 more elements
A circuit, comprising:
- means for generating one or more opcodes to control one or more timing and/or voltage characteristics of signals carried by a plurality of links of a device-to-device interface (DDI);
- means for transmitting, to a plurality of interface control circuits, the one or more opcodes, wherein each interface control circuit of the plurality of interface control circuits corresponds to a respective link of the plurality of links of the DDI;
- and
- means, at each respective interface control circuit of the plurality of interface control circuits, for:
- generating one or more interface adjustment signals in response to the one or more opcodes transmitted by the means for transmitting;
- and
- altering, using the one or more interface adjustment signals, one or more characteristics of one or more signals coupled to the respective interface control circuit;
- where each of the plurality of interface control circuits controls one or more timing and/or voltage characteristics of one or more signals carried by a respective link of the device-to-device interface (DDI).
5 more elements
Dependencies are inferred from the claim text.