System and methods for completing a cascaded clock ring bus

A cascaded clock ring network comprising:

• a clock signal path that transmits a source clock signal through a plurality of series-connected processing nodes, from a first processing node to a last processing node, wherein the last processing node provides the transmitted source clock signal as an end clock signal;
• a data path that transmits data values through the plurality of processing nodes in response to the transmitted source clock signal, from the first processing node to the last processing node, wherein the last processing node provides the transmitted data values as end data values;
• and
• a first-in first-out (FIFO) memory that writes the end data values in response to the end clock signal, and reads the end data values previously written to the FIFO memory to the first processing node in response to the source clock signal, wherein the FIFO memory stores each of the end data values for a valid data window period, the cascaded clock ring network further comprising means for initiating read operations to the FIFO memory near a center of each valid data window period.

A cascaded clock ring network comprising:

• a clock signal path that transmits a source clock signal through a plurality of series-connected processing nodes, from a first processing node to a last processing node, wherein the last processing node provides the transmitted source clock signal as an end clock signal;
• a data path that transmits data values through the plurality of processing nodes in response to the transmitted source clock signal, from the first processing node to the last processing node, wherein the last processing node provides the transmitted data values as end data values;
• a first-in first-out (FIFO) memory that writes the end data values in response to the end clock signal, and reads the end data values previously written to the FIFO memory to the first processing node in response to the source clock signal;
• and
• a control circuit for periodically measuring a delay associated with the clock signal path or the data path, and determining whether the periodically measured delays change by more than a threshold value, wherein the control circuit is configured to reset the FIFO memory in response to determining that the periodically measured delays change by more than the threshold value.

A cascaded clock ring network comprising:

• a clock signal path that transmits a source clock signal through a plurality of series-connected processing nodes, from a first processing node to a last processing node, wherein the last processing node provides the transmitted source clock signal as an end clock signal;
• a data path that transmits data values through the plurality of processing nodes in response to the transmitted source clock signal, from the first processing node to the last processing node, wherein the last processing node provides the transmitted data values as end data values;
• a first-in first-out (FIFO) memory that writes the end data values in response to the end clock signal, and reads the end data values previously written to the FIFO memory to the first processing node in response to the source clock signal;
• and
• a control circuit for periodically measuring a delay associated with the clock signal path or the data path, and determining whether the periodically measured delays change by more than a threshold value, wherein the control circuit includes an adjustable counter for selecting the period of the periodically measured delays.

A method of operating a cascaded clock ring network comprising:

• transmitting a source clock signal on a clock signal path through a plurality of series-connected processing nodes, from a first processing node to a last processing node, wherein the last processing node provides the transmitted source clock signal as an end clock signal;
• transmitting data values on a data path through the plurality of processing nodes in response to the transmitted source clock signal, from the first processing node to the last processing node, wherein the last processing node provides the transmitted data values as end data values;
• writing the end data values to a first-in first-out (FIFO) memory in response to the end clock signal;
• and
• reading the end data values previously written to the FIFO memory to the first processing node in response to the source clock signal;
• and
• synchronizing the writing and reading of the end data values to ensure that a plurality of the end data values are initially written into the FIFO memory before an end data value is read from the FIFO memory.

A method of operating a cascaded clock ring network comprising:

• transmitting a source clock signal on a clock signal path through a plurality of series-connected processing nodes, from a first processing node to a last processing node, wherein the last processing node provides the transmitted source clock signal as an end clock signal;
• transmitting data values on a data path through the plurality of processing nodes in response to the transmitted source clock signal, from the first processing node to the last processing node, wherein the last processing node provides the transmitted data values as end data values;
• writing the end data values to a first-in first-out (FIFO) memory in response to the end clock signal;
• and
• reading the end data values previously written to the FIFO memory to the first processing node in response to the source clock signal;
• storing each of the end data values in the FIFO memory for a valid data window period;
• and
• initiating read operations to the FIFO memory near a center of each valid data window period.