Self-test of an asynchronous circuit
AssigneeCryptography Research, Inc.
InventorMatthew Pond Baker
Life of this patent
Estimating the term…
Abstract
An indication of an operating mode of an asynchronous circuit may be received. A determination may be made as to whether the operating mode of the asynchronous circuit corresponds to a self-test of the asynchronous circuit. In response to determining that the operating mode of the asynchronous circuit corresponds to the self-test, a first clock signal may be provided to a first portion of a self-test component in a feedback path of the asynchronous circuit and a second clock signal may be provided to a second portion of the self-test component in the feedback path of the asynchronous circuit. Furthermore, a test value may be generated based on the first clock signal and the second clock signal.
Claims20
A method comprising:
- receiving, by a first circuit, an indication of an operating mode of an asynchronous circuit;
- determining, by the first circuit, that the operating mode of the asynchronous circuit corresponds to a self-test of the asynchronous circuit;
- in response to determining that the operating mode of the asynchronous circuit corresponds to the self-test, providing, by the first circuit, a first clock signal to a first portion of a second circuit in a feedback path of the asynchronous circuit and a second clock signal to a second portion of the second circuit in the feedback path of the asynchronous circuit;
- and
- generating, by the asynchronous circuit, a test value based on the first clock signal and the second clock signal.
An integrated circuit comprising:
- an asynchronous circuit comprising a self-test circuit in a feedback path of the asynchronous circuit;
- and
- a controller circuit, operatively coupled with the asynchronous circuit, to:
- receive an indication of an operating mode of the asynchronous circuit;
- determine that the operating mode of the asynchronous circuit corresponds to a self-test of the asynchronous circuit;
- and
- in response to determining that the operating mode of the asynchronous circuit corresponds to the self-test, provide a first clock signal to a first portion of the self-test circuit in the feedback path of the asynchronous circuit and a second clock signal to a second portion of the self-test circuit in the feedback path of the asynchronous circuit, wherein the asynchronous circuit generates a test value based on the first clock signal and the second clock signal.
A system comprising:
- a memory;
- and
- a processing device, operatively coupled with the memory, the processing device comprising a first circuit, a self-test circuit, and an asynchronous circuit, the processing device to:
- receive, by the first circuit, an indication of an operating mode of the asynchronous circuit;
- determine, by the first circuit that the operating mode of the asynchronous circuit corresponds to a self-test of the asynchronous circuit;
- in response to determining that the operating mode of the asynchronous circuit corresponds to the self-test, provide, by the first circuit, a first clock signal to a first portion of the self-test circuit in a feedback path of the asynchronous circuit and a second clock signal to a second portion of the self-test circuit in the feedback path of the asynchronous circuit;
- and
- generate, by the asynchronous circuit, a test value based on the first clock signal and the second clock signal.
Dependencies are inferred from the claim text.