3D tap and scan port architectures

An integrated circuit die comprising:

• a first surface including first parallel test input contact points, first parallel test output contact points, a test clock in contact point, a test mode select in contact point, a test reset in contact point, a first test data in contact point, and a first test data out contact point;
• a second surface opposite the first surface, the second surface including second parallel test output contact points coupled with the first parallel test input contact points, second parallel test input contact points coupled with the first parallel test output contact points, a test clock out contact point coupled with the test clock in contact point, a test mode select out contact point coupled with the test mode select in contact point, a test reset out contact point coupled with the test reset in contact point, a second test data out contact point coupled with the first test data in contact point, a second test data in contact point coupled with the first test data out contact point, and an UP contact point;
• test circuitry having an input coupled to the test clock in contact point, an input coupled to the test mode select in contact point, an input coupled to the test reset in contact point, and an input coupled to the first test data in contact point, and having control outputs;
• scan circuitry having an input coupled to the first test data in contact point, an output coupled to the first and second test data out contact points, and having control inputs coupled with the control outputs of the test circuitry;
• and
• UP control circuitry including:
• a gate having an input coupled with the test reset in contact point and having an output;
• and
• a flip flop having inputs coupled to the control outputs of the test circuitry, having an inverted input coupled to the output of the gate, and having an output coupled with the UP contact point.