System-on-chip including CPU operating as debug host and method of operating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsHo-sung Kim, Chang-ki Kim, Byeong-jin Kim
Life of this patent
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Abstract
Provided is a method of operating a system-on-chip (SoC) including a plurality of CPUs. The method includes: receiving a debug request by a first CPU of the CPUs; outputting a first signal to the CPUs by the first CPU in response to the debug request; selecting a second CPU from the CPUs to control the debugging based on the first signal; and performing a debug operation by selecting a debug target block by the second CPU.
Claims17
A method of operating a system-on-chip (SoC) that includes at least a first central processing unit (CPU) and a second CPU, each of the first and second CPUs being operable to perform a debug operation on a debug target block that is a different functional block of the SoC, the method comprising:
- receiving a debug request by the first CPU;
- outputting a first signal by the first CPU based on the debug request, the first signal being an event signal to initiate debugging;
- broadcasting the event signal to each of the first and second CPUs;
- selecting the second CPU as a debug host that performs a debug operation on the debug target block;
- and
- performing the debug operation on the debug target block by the second CPU, wherein:
- selecting the second CPU includes selecting the second CPU based on a result of receiving the broadcasted event signal with respect to the first and second CPUs,
- the SoC includes a flag register storing flag information respectively corresponding to the first and second CPUs, and
- selecting the second CPU further includes:
- changing at least one of the flag information respectively corresponding to the first and second CPUs based on the received result;
- and
- selecting a CPU corresponding to the at least one of the changed flag information of the first and second CPUs as the second CPU.
A system-on-chip (SoC), comprising:
- a plurality of first functional blocks;
- a plurality of second functional blocks, each of the plurality of second functional blocks including:
- an event generation logic to output an event signal to initiate debugging, and
- a debug performing logic operable to perform a debug operation on a debug target block that is a different functional block of the SoC;
- and
- debug control logic to receive the event signal from a first one of the plurality of second functional blocks and to broadcast the event signal to the plurality of second functional blocks, wherein:
- a second one of the plurality of second functional blocks is selected based on result of receiving the broadcasted event signal with respect to the plurality of second functional blocks such that the second one of the plurality of second functional blocks operates as a debug host that performs the debug operation on the debug target block,
- the SoC includes a flag register storing flag information respectively corresponding to the first and second ones of the plurality of second functional blocks,
- at least one of the flag information corresponding to the first and second ones of the plurality of second functional blocks is changed based on the received result, and
- the second one of the plurality of second functional blocks is selected as the debug host in correspondence with the at least one of the changed flag information.
A system-on-chip (SoC), comprising:
- a plurality of processors, each of the processors being operable to perform a debug operation on a debug target block that is a different functional block of the SoC;
- a memory to store a debugging code;
- a debug control logic to receive an event signal from a second processor of the plurality of processors and to broadcast the event signal to the plurality of processors;
- first logic to select a first processor of the plurality of processors based on result of receiving the broadcasted event signal with respect to the plurality of processors such that the first processor operates as a debug host that performs a debug operation based on the debugging code;
- and
- a flag register storing flag information respectively corresponding to the first and second processors, wherein:
- at least one of the flag information corresponding to the first and second processors is changed based on the received result, and
- the first processor is selected as the debug host in correspondence with the at least one of the changed flag information.
Dependencies are inferred from the claim text.