Methods, systems, and computer readable media for de-interleaving data in a communication system

A method for de-interleaving data in a communication system, the method comprising:

• receiving, at each clock cycle of a plurality of clock cycles of the communication system, a bit lane of data on a data bus, each bit lane including Q valid bits of an interleaved packet of length E;
• placing, at each clock cycle, each of the Q valid bits into a respective bin of Q bins each having a bin width B;
• determining that the bins are full, and in response to determining that the bins are full, transferring contents of the bins into Q registers each having a register width B;
• and
• repeatedly receiving and placing data bits from the bit lanes into the bins and transferring the contents of the bins to the registers until at least E valid bits have been transferred to the registers;
• wherein receiving the bit lanes on the data bus comprises receiving the bit lanes from a Physical Downlink Shared Channel (PDSCH) of a 5G system.

A system for de-interleaving data in a communication system, the system comprising:

• a data bus;
• Q registers each having a register width B;
• and
• a receiver circuit configured for:
• receiving, at each clock cycle of a plurality of clock cycles of the communication system, a bit lane of data on the data bus, each bit lane including Q valid bits of an interleaved packet of length E;
• placing, at each clock cycle, each of the Q valid bits into a respective bin of Q bins each having a bin width equal to the register width B;
• determining that the bins are full, and in response to determining that the bins are full, transferring contents of the bins into the registers, and after transferring the contents of the bins into the registers, storing the contents of the registers into Q segments of a memory area, each segment being sized to store E/Q bits;
• reading a de-interleaved packet from the Q segments of the memory area, wherein reading the de-interleaved packet comprises reading, at a first memory location, a number of stored bits and incrementing a counter for each bit read;
• and
• repeatedly receiving and placing data bits from the bit lanes into the bins and transferring the contents of the bins to the registers until at least E valid bits have been transferred to the registers.

A system for de-interleaving data in a communication system, the system comprising:

• a data bus;
• Q registers each having a register width B;
• and
• a receiver circuit configured for:
• receiving, at each clock cycle of a plurality of clock cycles of the communication system, a bit lane of data on the data bus, each bit lane including Q valid bits of an interleaved packet of length E;
• placing, at each clock cycle, each of the Q valid bits into a respective bin of Q bins each having a bin width equal to the register width B;
• determining that the bins are full, and in response to determining that the bins are full, transferring contents of the bins into the registers;
• and
• repeatedly receiving and placing data bits from the bit lanes into the bins and transferring the contents of the bins to the registers until at least E valid bits have been transferred to the registers;
• wherein receiving the bit lanes on the data bus comprises receiving the bit lanes from a Physical Downlink Shared Channel (PDSCH) of a 5G system.